Yield analysis for repairable embedded memories

A. Sehgal, A. Dubey, E.J. Marinissen, C. Wouters, H.P.E. Vranken, K. Chakrabarty

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureHoofdstukAcademicpeer review

5 Citaten (Scopus)


Repairable embedded memories help improve the overall yield of an IC. We have developed a yield analysis tool that provides realistic yield estimates for both single repairable memories, as well as for ICs containing multiple, possibly different, repairable embedded memories. Our approach uses pseudo-randomly generated fault bit-maps, which are based on memory area size, defect density, and fault distribution. In order to accommodate a wide range of industrial memory and redundancy organizations, we have developed a flexible memory model. It generalizes the traditional simple memory matrix model with partitioning into regions, grouping of columns and rows, and column-wise and row-wise coupling of the spares. Our tool is used to determine an optimal amount of spare columns and rows for a given memory, as well as to determine the effectiveness of various repair algorithms.
Originele taal-2Engels
TitelThe Eighth IEEE European Test Workshop, 2003. Proceedings
Plaats van productiePiscataway
UitgeverijInstitute of Electrical and Electronics Engineers
ISBN van geprinte versie0-7695-1908-3
StatusGepubliceerd - 2003
Extern gepubliceerdJa
Evenement8th IEEE European Test Workshop 2003 - Crowne Plaza Hotel, Maastricht, Nederland
Duur: 28 mei 200328 mei 2003
Congresnummer: 8


Congres8th IEEE European Test Workshop 2003
Verkorte titelETW'03
Internet adres


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