Wrapper design for the reuse of networks-on-chip as test access mechanism

A.M. Amory, K.G.W. Goossens, E.J. Marinissen, M. Lubaszewski, F. Moraes

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

35 Citaten (Scopus)


This paper proposes a wrapper design for interconnects with guaranteed bandwidth and latency services and on-chip protocol. We demonstrate that these interconnects abstract the interconnect details and provide predictability in the data transfer, which are desirable not only for the functional domain but also for the test application. The proposed wrapper is implemented in VHDL and integrated to the Æthereal NoC. The results show the impact of of bandwidth in the core test time. The wrapper area and core test time are compared with a wrapper design for dedicated TAM. © 2006 IEEE.
Originele taal-2Engels
Titel11th IEEE European Test Symposium, ETS 2006, 21 May 2006 through 21 May 2006, Southampton
Plaats van productiePiscataway
UitgeverijInstitute of Electrical and Electronics Engineers
ISBN van geprinte versie0-7695-2566-0
StatusGepubliceerd - 2006
Evenement11th IEEE European Test Symposium (ETS 2006) - Southampton, Verenigd Koninkrijk
Duur: 21 mei 200625 mei 2006
Congresnummer: 11


Congres11th IEEE European Test Symposium (ETS 2006)
Verkorte titelETS 2006
LandVerenigd Koninkrijk
AnderIEEE European Test Symposium, Southampton, UK
Internet adres


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