Voltage Stacking for Near/Sub-threshold Ultra-Low Power Microprocessor Systems

Kamlesh Singh; Barry de Bruin; Jos Huisken; Hailong Jiao; Henk Corporaal; Jose Pineda de Gyvez

doi:10.1109/S3S46989.2019.9320661

Voltage Stacking for Near/Sub-threshold Ultra-Low Power Microprocessor Systems

Kamlesh Singh, Barry de Bruin, Jos Huisken, Hailong Jiao, Henk Corporaal, Jose Pineda de Gyvez

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

Samenvatting

A three-layer voltage stacking system supporting near/sub-threshold region operations is proposed in this paper. A Pulpino micro-controller and a reconfigurable accelerator are put at the bottom and middle stacks, while SRAM arrays are placed on the top stack. The micro-controller and the accelerator operate in the near/sub-threshold voltage region by only using the leakage currents from the SRAM arrays on top. Instead of using complex voltage regulators, a simple current sink voltage controller and adaptive body-bias based voltage controller with low area and energy overhead are used to stabilize the intermediate voltage rails between the top and middle as well as between the middle and bottom voltage stacks. To the best of our knowledge, this is the first work proposing voltage stacking for near/sub-threshold systems. Implemented in a 28-nm FDSOI CMOS technology, the proposed voltage stacking system reduces the power consumption by up to 30% as compared to the conventional flat implementation.

Originele taal-2	Engels
Titel	2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019
Uitgeverij	Institute of Electrical and Electronics Engineers
Aantal pagina's	2
ISBN van elektronische versie	9781728135236
DOI's	https://doi.org/10.1109/S3S46989.2019.9320661
Status	Gepubliceerd - 14 okt. 2019
Evenement	2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019 - San Jose, Verenigde Staten van Amerika Duur: 14 okt. 2019 → 17 okt. 2019

Congres

Congres	2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019
Land/Regio	Verenigde Staten van Amerika
Stad	San Jose
Periode	14/10/19 → 17/10/19

Financiering

This work was partially funded by the Dutch STW project 14714 BrainWave.

Toegang tot document

10.1109/S3S46989.2019.9320661

Andere bestanden en links

Link to publication in Scopus

Brainwave
Huisken, J. A. (Projectmedewerker), Jiao, H. (Project Manager), Singh, K. (Projectmedewerker), Sánchez Martín, V. (Project Manager), de Bruin, B. (Projectmedewerker), van der Hagen, D. (Project communicatie medewerker) & de Mol-Regels, M. (Project communicatie medewerker)
1/09/16 → 30/11/21
Project: Onderzoek direct
Wearable Brainwave Processing Platform
Bergmans, J. W. M. (Project Manager), van der Hagen, D. (Project communicatie medewerker), Sánchez Martín, V. (Program Manager), Corporaal, H. (Projectmedewerker), Pineda de Gyvez, J. (Projectmedewerker) & Huisken, J. A. (Projectmedewerker)
1/09/16 → 30/11/21
Project: Onderzoek direct

Citeer dit

Singh, K., de Bruin, B., Huisken, J., Jiao, H., Corporaal, H., & de Gyvez, J. P. (2019). Voltage Stacking for Near/Sub-threshold Ultra-Low Power Microprocessor Systems. In 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019 Artikel 9320661 Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/S3S46989.2019.9320661

@inproceedings{b6e4c067e7374425a2196bdb2a0306ff,

title = "Voltage Stacking for Near/Sub-threshold Ultra-Low Power Microprocessor Systems",

abstract = "A three-layer voltage stacking system supporting near/sub-threshold region operations is proposed in this paper. A Pulpino micro-controller and a reconfigurable accelerator are put at the bottom and middle stacks, while SRAM arrays are placed on the top stack. The micro-controller and the accelerator operate in the near/sub-threshold voltage region by only using the leakage currents from the SRAM arrays on top. Instead of using complex voltage regulators, a simple current sink voltage controller and adaptive body-bias based voltage controller with low area and energy overhead are used to stabilize the intermediate voltage rails between the top and middle as well as between the middle and bottom voltage stacks. To the best of our knowledge, this is the first work proposing voltage stacking for near/sub-threshold systems. Implemented in a 28-nm FDSOI CMOS technology, the proposed voltage stacking system reduces the power consumption by up to 30% as compared to the conventional flat implementation.",

author = "Kamlesh Singh and {de Bruin}, Barry and Jos Huisken and Hailong Jiao and Henk Corporaal and {de Gyvez}, {Jose Pineda}",

year = "2019",

month = oct,

day = "14",

doi = "10.1109/S3S46989.2019.9320661",

language = "English",

booktitle = "2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019 ; Conference date: 14-10-2019 Through 17-10-2019",

}

Singh, K, de Bruin, B, Huisken, J, Jiao, H , Corporaal, H & de Gyvez, JP 2019, Voltage Stacking for Near/Sub-threshold Ultra-Low Power Microprocessor Systems. in 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019., 9320661, Institute of Electrical and Electronics Engineers, 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019, San Jose, Verenigde Staten van Amerika, 14/10/19. https://doi.org/10.1109/S3S46989.2019.9320661

Voltage Stacking for Near/Sub-threshold Ultra-Low Power Microprocessor Systems. / Singh, Kamlesh; de Bruin, Barry; Huisken, Jos et al.
2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019. Institute of Electrical and Electronics Engineers, 2019. 9320661.

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

TY - GEN

T1 - Voltage Stacking for Near/Sub-threshold Ultra-Low Power Microprocessor Systems

AU - Singh, Kamlesh

AU - de Bruin, Barry

AU - Huisken, Jos

AU - Jiao, Hailong

AU - Corporaal, Henk

AU - de Gyvez, Jose Pineda

PY - 2019/10/14

Y1 - 2019/10/14

N2 - A three-layer voltage stacking system supporting near/sub-threshold region operations is proposed in this paper. A Pulpino micro-controller and a reconfigurable accelerator are put at the bottom and middle stacks, while SRAM arrays are placed on the top stack. The micro-controller and the accelerator operate in the near/sub-threshold voltage region by only using the leakage currents from the SRAM arrays on top. Instead of using complex voltage regulators, a simple current sink voltage controller and adaptive body-bias based voltage controller with low area and energy overhead are used to stabilize the intermediate voltage rails between the top and middle as well as between the middle and bottom voltage stacks. To the best of our knowledge, this is the first work proposing voltage stacking for near/sub-threshold systems. Implemented in a 28-nm FDSOI CMOS technology, the proposed voltage stacking system reduces the power consumption by up to 30% as compared to the conventional flat implementation.

AB - A three-layer voltage stacking system supporting near/sub-threshold region operations is proposed in this paper. A Pulpino micro-controller and a reconfigurable accelerator are put at the bottom and middle stacks, while SRAM arrays are placed on the top stack. The micro-controller and the accelerator operate in the near/sub-threshold voltage region by only using the leakage currents from the SRAM arrays on top. Instead of using complex voltage regulators, a simple current sink voltage controller and adaptive body-bias based voltage controller with low area and energy overhead are used to stabilize the intermediate voltage rails between the top and middle as well as between the middle and bottom voltage stacks. To the best of our knowledge, this is the first work proposing voltage stacking for near/sub-threshold systems. Implemented in a 28-nm FDSOI CMOS technology, the proposed voltage stacking system reduces the power consumption by up to 30% as compared to the conventional flat implementation.

UR - http://www.scopus.com/inward/record.url?scp=85100853685&partnerID=8YFLogxK

U2 - 10.1109/S3S46989.2019.9320661

DO - 10.1109/S3S46989.2019.9320661

M3 - Conference contribution

AN - SCOPUS:85100853685

BT - 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019

PB - Institute of Electrical and Electronics Engineers

T2 - 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019

Y2 - 14 October 2019 through 17 October 2019

ER -

Voltage Stacking for Near/Sub-threshold Ultra-Low Power Microprocessor Systems

Samenvatting

Congres

Financiering

Toegang tot document

Andere bestanden en links

Vingerafdruk

Projecten

Brainwave

Wearable Brainwave Processing Platform

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