Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation

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2 Citaten (Scopus)

Samenvatting

Integrated systems operating in the near/sub-threshold region offer low power and energy consumption. Such systems, however, typically suffer from low efficiency in power delivery, thereby leading to ineffective power savings. In this paper, a voltage stacking system with a RISC-V microcontroller Pulpino at the bottom voltage stack and memory arrays on the top stack is proposed. The memory arrays operate at 0.7 V supply voltage, while the microcontroller operate at 0.4 V supply voltage (near/sub-threshold region) by using the leakage currents from the memory arrays. Instead of using complex voltage regulators, a simple current sink voltage controller with low area and energy overheads is used to stabilize the intermediate voltage rail between the top and bottom power domains. To the best of our knowledge, this is the first work proposing voltage stacking for near/sub-threshold systems. Implemented in a 28-nm FDSOI CMOS technology, the proposed voltage stacking system reduces the power consumption by up to 43% as compared to the conventional implementation in a flat voltage domain.

Originele taal-2Engels
TitelProceedings - 32nd IEEE International System on Chip Conference, SOCC 2019
RedacteurenDanella Zhao, Arindam Basu, Magdy Bayoumi, Gwee Bah Hwee, Ge Tong, Ramalingam Sridhar
UitgeverijIEEE Computer Society
Pagina's370-375
Aantal pagina's6
ISBN van elektronische versie9781728134826
DOI's
StatusGepubliceerd - sep 2019
Evenement32nd IEEE International System on Chip Conference, SOCC 2019 - Singapore, Singapore
Duur: 3 sep 20196 sep 2019

Congres

Congres32nd IEEE International System on Chip Conference, SOCC 2019
Land/RegioSingapore
StadSingapore
Periode3/09/196/09/19

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