This tutorial paper surveys the past 20 years of near/sub-threshold digital integrated circuit design. Most of the chips have been highly characterized for voltage scaling down to near/sub-threshold, and a significantly custom design effort has been reported to achieve reliable operation. In this tutorial, we address the challenges of process variations and discuss the circuits and methods used over the years to minimize this impact. We discuss the advantages of standard-cell library design and provide a more involved pruning method to improve performance and robustness. Finally, we discuss the developments of the usually ignored power delivery techniques for near/sub-threshold circuits. We motivate the use of voltage stacking as a new power delivery technique for near/sub-threshold. This paper provides the basic enablement approaches for designing a chip operating in the near/sub-threshold region based on our experience.
|Tijdschrift||IEEE Transactions on Circuits and Systems II: Express Briefs|
|Nummer van het tijdschrift||1|
|Vroegere onlinedatum||30 nov 2020|
|Status||Gepubliceerd - 1 jan 2021|