The integration and test phase of a new type of a complex system, like an ASML waferscanner, takes up to 50% of the development duration. During this phase, many components are delivered with different delivery times that often change. These components are tested and integrated into a working system. The tests that can be performed in a test phase depend on the integrated components and therefore on the integration sequence. These dependencies and other disturbances make the integration and test phase hard to plan. In practice, hand-made integration and tests plans are often sub-optimal and incomplete. This sub-optimality was already shown by a previous case-study where the optimization of a test phase reduced the test duration up to 30% [Bits&Chips conference 2005].In our work we develop simple models and tools that automatically analyze, compare and optimize integration and test plans. The overall goal of these models and tools is to create an optimal integration and test plan which takes the least amount of time to execute. In this presentation we will introduce the models and tools that have been developed to reach this goal. Also, we will present the results of several case-studies that have been performed at ASML to show the benefits of these models and tools.Tangram projectThe Tangram project is a research project with the goal to develop methods that reduce test and integration time for multidisciplinary systems, like the ASML waferscanner. The partners in the Tangram project are ASML, as carrying industrial partner, 3 Dutch universities: TU/e, RU and TUD, TNO, Science & Technology and the Embedded Systems Institute as project coordinator. The research presented in this presentation is a part of the subproject ‘Integration and test strategy’. More information can be found on www.esi.nl/tangram.
|Titel||Bits&Chips test event|
|Plaats van productie||Netherlands, Eindhoven|
|Status||Gepubliceerd - 2006|