Testing 3D chips containing through-silicon vias

E.J. Marinissen, Y. Zorian

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureHoofdstukAcademicpeer review

260 Citaten (Scopus)
106 Downloads (Pure)


Today's miniaturization and performance requirements result in the usage of high-density integration and packaging technologies, such as 3D Stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs). Due to their advanced manufacturing processes and physical access limitations, the complexity and cost associated with testing this type of 3D-SICs are considered major challenges. This Embedded Tutorial provides an overview of the manufacturing steps of TSV-based 3D chips and their associated test challenges. It discusses the necessary flows for wafer-level and package-level tests, the challenges with respect to test contents and wafer-level probe access, and the on-chip DfT infrastructure required for 3D-SICs.
Originele taal-2Engels
Titel2009 International Test Conference
Plaats van productiePiscataway
UitgeverijInstitute of Electrical and Electronics Engineers
Aantal pagina's11
ISBN van geprinte versie978-1-4244-4868-5
StatusGepubliceerd - nov 2009
Extern gepubliceerdJa
Evenement2009 International Test Conference (ITC 2009) - Austin, Verenigde Staten van Amerika
Duur: 1 nov 20096 nov 2009


Congres2009 International Test Conference (ITC 2009)
Verkorte titelITC 2009
Land/RegioVerenigde Staten van Amerika


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