Synchronised 4-phase resonant power clock supply for energy efficient adiabatic logic

Nicolas Jeanniot; Gaël Pillonnet; Pascal Nouet; Nadine Azemard; Aida Todri-Sanial

doi:10.1109/ICRC.2017.8123661

Synchronised 4-phase resonant power clock supply for energy efficient adiabatic logic

Nicolas Jeanniot, Gaël Pillonnet, Pascal Nouet, Nadine Azemard, Aida Todri-Sanial

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

12 Citaten (Scopus)

Samenvatting

Adiabatic logic is an alternative architecture design style to reduce the power consumption of digital cores by using AC power supply instead of DC ones. The energy saving of the digital gates is strongly related to the efficiency of adiabatic AC power supplies. In this paper, we propose a resonant reversible power-clock supply design with four different phases. The resonance deviation between the four power-clock supplies is synchronized thanks to 12 control signals (3 controls signals per power-clock supply).We derive the energy dissipation of a 4-stage PFAL pipeline circuit supplied with the proposed resonant powerclock supply, which can dissipate up to 2.9 times less energy than a non-Adiabatic CMOS pipeline.

Originele taal-2	Engels
Titel	2017 IEEE International Conference on Rebooting Computing, ICRC 2017 - Proceedings
Uitgeverij	Institute of Electrical and Electronics Engineers
Pagina's	1-6
Aantal pagina's	6
ISBN van elektronische versie	9781538615539
DOI's	https://doi.org/10.1109/ICRC.2017.8123661
Status	Gepubliceerd - 28 nov. 2017
Extern gepubliceerd	Ja
Evenement	2017 IEEE International Conference on Rebooting Computing, ICRC 2017 - Washington, Verenigde Staten van Amerika Duur: 8 nov. 2017 → 9 nov. 2017

Congres

Congres	2017 IEEE International Conference on Rebooting Computing, ICRC 2017
Land/Regio	Verenigde Staten van Amerika
Stad	Washington
Periode	8/11/17 → 9/11/17

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©2017 IEEE.

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title = "Synchronised 4-phase resonant power clock supply for energy efficient adiabatic logic",

abstract = "Adiabatic logic is an alternative architecture design style to reduce the power consumption of digital cores by using AC power supply instead of DC ones. The energy saving of the digital gates is strongly related to the efficiency of adiabatic AC power supplies. In this paper, we propose a resonant reversible power-clock supply design with four different phases. The resonance deviation between the four power-clock supplies is synchronized thanks to 12 control signals (3 controls signals per power-clock supply).We derive the energy dissipation of a 4-stage PFAL pipeline circuit supplied with the proposed resonant powerclock supply, which can dissipate up to 2.9 times less energy than a non-Adiabatic CMOS pipeline.",

keywords = "Adiabatic Logic, Energy Efficiency, Power-Clock Supply, Resonant Power Supply, Reversible Power Supply",

author = "Nicolas Jeanniot and Ga{\"e}l Pillonnet and Pascal Nouet and Nadine Azemard and Aida Todri-Sanial",

note = "Publisher Copyright: {\textcopyright}2017 IEEE.; 2017 IEEE International Conference on Rebooting Computing, ICRC 2017 ; Conference date: 08-11-2017 Through 09-11-2017",

year = "2017",

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doi = "10.1109/ICRC.2017.8123661",

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Jeanniot, N, Pillonnet, G, Nouet, P, Azemard, N & Todri-Sanial, A 2017, Synchronised 4-phase resonant power clock supply for energy efficient adiabatic logic. in 2017 IEEE International Conference on Rebooting Computing, ICRC 2017 - Proceedings. Institute of Electrical and Electronics Engineers, blz. 1-6, 2017 IEEE International Conference on Rebooting Computing, ICRC 2017, Washington, Verenigde Staten van Amerika, 8/11/17. https://doi.org/10.1109/ICRC.2017.8123661

Synchronised 4-phase resonant power clock supply for energy efficient adiabatic logic. / Jeanniot, Nicolas; Pillonnet, Gaël; Nouet, Pascal et al.
2017 IEEE International Conference on Rebooting Computing, ICRC 2017 - Proceedings. Institute of Electrical and Electronics Engineers, 2017. blz. 1-6.

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

TY - GEN

T1 - Synchronised 4-phase resonant power clock supply for energy efficient adiabatic logic

AU - Jeanniot, Nicolas

AU - Pillonnet, Gaël

AU - Nouet, Pascal

AU - Azemard, Nadine

AU - Todri-Sanial, Aida

PY - 2017/11/28

Y1 - 2017/11/28

N2 - Adiabatic logic is an alternative architecture design style to reduce the power consumption of digital cores by using AC power supply instead of DC ones. The energy saving of the digital gates is strongly related to the efficiency of adiabatic AC power supplies. In this paper, we propose a resonant reversible power-clock supply design with four different phases. The resonance deviation between the four power-clock supplies is synchronized thanks to 12 control signals (3 controls signals per power-clock supply).We derive the energy dissipation of a 4-stage PFAL pipeline circuit supplied with the proposed resonant powerclock supply, which can dissipate up to 2.9 times less energy than a non-Adiabatic CMOS pipeline.

AB - Adiabatic logic is an alternative architecture design style to reduce the power consumption of digital cores by using AC power supply instead of DC ones. The energy saving of the digital gates is strongly related to the efficiency of adiabatic AC power supplies. In this paper, we propose a resonant reversible power-clock supply design with four different phases. The resonance deviation between the four power-clock supplies is synchronized thanks to 12 control signals (3 controls signals per power-clock supply).We derive the energy dissipation of a 4-stage PFAL pipeline circuit supplied with the proposed resonant powerclock supply, which can dissipate up to 2.9 times less energy than a non-Adiabatic CMOS pipeline.

KW - Adiabatic Logic

KW - Energy Efficiency

KW - Power-Clock Supply

KW - Resonant Power Supply

KW - Reversible Power Supply

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U2 - 10.1109/ICRC.2017.8123661

DO - 10.1109/ICRC.2017.8123661

M3 - Conference contribution

SP - 1

EP - 6

BT - 2017 IEEE International Conference on Rebooting Computing, ICRC 2017 - Proceedings

PB - Institute of Electrical and Electronics Engineers

T2 - 2017 IEEE International Conference on Rebooting Computing, ICRC 2017

Y2 - 8 November 2017 through 9 November 2017

ER -

Synchronised 4-phase resonant power clock supply for energy efficient adiabatic logic

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