Successive approximation analog-to-digital converters

Successive-approximation register analog-to-digital converters (SAR ADCs) have been around for a long time, but they have recently received a lot of attention due to the advantages of process scaling and recent architectural innovations, leading to improvements in power efficiency and conversion speed. For illustration, Figure 1 shows a collection of data converters in terms of energy per conversion (which is the power consumption P divided by the sampling rate fs) and accuracy, expressed as signal-to-noise-and-distortion ratio (SNDR), based on data from [1]. As one can see, SAR ADCs are very power efficient compared to other architectures for medium accuracies between 40 and 70 dB of SNDR. In terms of speed, SAR ADCs have managed to reach sampling rates of up to 90 GS/s when time interleaved [2]. One of the reasons SAR ADCs are doing so well is because they use simple analog and digital circuits that tend to scale well and benefit from newer process technologies. Moreover, the simple structure often allows operation at reduced supply levels, which can save additional power. In this article, we will discuss the basic design aspects of SAR ADCs and give a short overview of state-of-the-art designs and future trends.