Abstract A new approach for analog fault modeling and simulation is presented. The proposed approach utilizes the sensitivity of the circuit’s DC node voltages to the process variations and consequently the current deviance so as to differentiate the faulty behavior. A systematic method is proposed for the fault discrimination to minimize the probability that the circuit is accepted as a fault-free when it is faulty. Tests are generated and evaluated taking into account the potential fault masking effects of process spread on the faulty circuit responses. The introduced fault model is validated on a time-interleaved sample-and-hold circuit. Simulation results demonstrate the effectiveness of the model.
|Tijdschrift||Journal of Electronic Testing : Theory and Applications|
|Nummer van het tijdschrift||4-6|
|Status||Gepubliceerd - 2006|