SIMD with delay line in instruction bus

The ID discloses a SIMD processor array havint two segmented unidirectional busses for communicating data between the various processing elements (PEs). In addition, the instruction bus of the PEs comprises delay elements to facilitate the execution of instructions by different PEs at different points in time. In a preferred embodiment, the delay elements in the instruction bus may be bypassed to enable two operational modes of the SIMD: one mode in which all PEs simultaneously execute the same instruction and one mode in which the instructions are delayed from one PE to another. According to another aspect of the invention, a scheduler for such an SIMD architecture is provided for soloving data dependency conflicts by scheduling the full set of instructions for a given PE, and deriving the scheduling of all other PEs as a function of the appropriate delay from the schedule for the given PE