SIMD memory circuit and methodology to support upsampling, downsampling and transposition

D. Kampen, van (Uitvinder), C.H. Berkel, van (Uitvinder), S.L.M. Goossens (Uitvinder), W.E.H. Kloosterhuis (Uitvinder), C. Zissulecsu-Ianculescu (Uitvinder)

Onderzoeksoutput: OctrooiOctrooi-publicatie

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An apparatus and method for creation of reordered vectors from sequential input data for block based decimation, filtering, interpolation and matrix transposition using a memory circuit for a Single Instruction, Multiple Data (SIMD) Digital Signal Processor (DSP). This memory circuit includes a two-dimensional storage array, a rotate-and-distribute unit, a read-controller and a write to controller, to map input vectors containing sequential data elements in columns of the two-dimensional array and extract reordered target vectors from this array. The data elements and memory configuration are received from the SIMD DSP.
Originele taal-2Engels
OctrooinummerUS20130091339
Prioriteitsdatum5/10/11
StatusGepubliceerd - 11 apr 2013

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Also published as:
WO2013050494 (A1)

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