TY - PAT
T1 - SIMD memory circuit and methodology to support upsampling, downsampling and transposition
AU - Kampen, van, D.
AU - Berkel, van, C.H.
AU - Goossens, S.L.M.
AU - Kloosterhuis, W.E.H.
AU - Zissulecsu-Ianculescu, C.
N1 - Also published as:
WO2013050494 (A1)
PY - 2013/4/11
Y1 - 2013/4/11
N2 - An apparatus and method for creation of reordered vectors from sequential input data for block based decimation, filtering, interpolation and matrix transposition using a memory circuit for a Single Instruction, Multiple Data (SIMD) Digital Signal Processor (DSP). This memory circuit includes a two-dimensional storage array, a rotate-and-distribute unit, a read-controller and a write to controller, to map input vectors containing sequential data elements in columns of the two-dimensional array and extract reordered target vectors from this array. The data elements and memory configuration are received from the SIMD DSP.
AB - An apparatus and method for creation of reordered vectors from sequential input data for block based decimation, filtering, interpolation and matrix transposition using a memory circuit for a Single Instruction, Multiple Data (SIMD) Digital Signal Processor (DSP). This memory circuit includes a two-dimensional storage array, a rotate-and-distribute unit, a read-controller and a write to controller, to map input vectors containing sequential data elements in columns of the two-dimensional array and extract reordered target vectors from this array. The data elements and memory configuration are received from the SIMD DSP.
UR - http://worldwide.espacenet.com/publicationDetails/biblio?DB=EPODOC&II=0&ND=3&adjacent=true&locale=nl_NL&FT=D&date=20130411&CC=US&NR=2013091339A1&KC=A1
M3 - Patent publication
M1 - US20130091339
ER -