Sigma-delta ADC clock jitter in digitally implemented receiver architectures

Paul T.M. van Zeijl; Robert H.M. van Veldhoven; Peter A.C.M. Nuijten

doi:10.1109/ECWT.2006.280423

Sigma-delta ADC clock jitter in digitally implemented receiver architectures

Paul T.M. van Zeijl
, Robert H.M. van Veldhoven
, Peter A.C.M. Nuijten

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

3 Citaten (Scopus)

Samenvatting

The analog-to-digital (AD) converter in modern multi-band multi-mode software defined radios plays a very important role. This paper will show how the specifications for the clock of a sigma-delta AD-converters can be derived. In contrast to literature, where clock jitter (in ps_rms) is specified, a different approach will be taken, in which the frequency dependent spurious of the clock signal can be calculated in the case of a GSM receiver.

Originele taal-2	Engels
Titel	Proceedings of the 9th European Conference on Wireless Technology, ECWT 2006
Uitgeverij	Institute of Electrical and Electronics Engineers
Pagina's	16-18
Aantal pagina's	3
ISBN van geprinte versie	2-9600551-5-2
DOI's	https://doi.org/10.1109/ECWT.2006.280423
Status	Gepubliceerd - 15 jan. 2007
Extern gepubliceerd	Ja
Evenement	9th European Conference on Wireless Technology, ECWT 2006 - Manchester, Verenigd Koninkrijk Duur: 10 sep. 2006 → 12 sep. 2006

Congres

Congres	9th European Conference on Wireless Technology, ECWT 2006
Land/Regio	Verenigd Koninkrijk
Stad	Manchester
Periode	10/09/06 → 12/09/06

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title = "Sigma-delta ADC clock jitter in digitally implemented receiver architectures",

abstract = "The analog-to-digital (AD) converter in modern multi-band multi-mode software defined radios plays a very important role. This paper will show how the specifications for the clock of a sigma-delta AD-converters can be derived. In contrast to literature, where clock jitter (in psrms) is specified, a different approach will be taken, in which the frequency dependent spurious of the clock signal can be calculated in the case of a GSM receiver.",

author = "\{van Zeijl\}, \{Paul T.M.\} and \{van Veldhoven\}, \{Robert H.M.\} and Nuijten, \{Peter A.C.M.\}",

year = "2007",

month = jan,

day = "15",

doi = "10.1109/ECWT.2006.280423",

language = "English",

isbn = "2-9600551-5-2",

pages = "16--18",

booktitle = "Proceedings of the 9th European Conference on Wireless Technology, ECWT 2006",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "9th European Conference on Wireless Technology, ECWT 2006 ; Conference date: 10-09-2006 Through 12-09-2006",

}

van Zeijl, PTM, van Veldhoven, RHM & Nuijten, PACM 2007, Sigma-delta ADC clock jitter in digitally implemented receiver architectures. in Proceedings of the 9th European Conference on Wireless Technology, ECWT 2006., 4057426, Institute of Electrical and Electronics Engineers, blz. 16-18, 9th European Conference on Wireless Technology, ECWT 2006, Manchester, Verenigd Koninkrijk, 10/09/06. https://doi.org/10.1109/ECWT.2006.280423

Sigma-delta ADC clock jitter in digitally implemented receiver architectures. / van Zeijl, Paul T.M.; van Veldhoven, Robert H.M.; Nuijten, Peter A.C.M.
Proceedings of the 9th European Conference on Wireless Technology, ECWT 2006. Institute of Electrical and Electronics Engineers, 2007. blz. 16-18 4057426.

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

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AB - The analog-to-digital (AD) converter in modern multi-band multi-mode software defined radios plays a very important role. This paper will show how the specifications for the clock of a sigma-delta AD-converters can be derived. In contrast to literature, where clock jitter (in psrms) is specified, a different approach will be taken, in which the frequency dependent spurious of the clock signal can be calculated in the case of a GSM receiver.

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Sigma-delta ADC clock jitter in digitally implemented receiver architectures

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