Shared interrupt multi-core architecture for low power applications

J.D. Echeverri Escobar (Uitvinder), J. Pineda de Gyvez (Uitvinder)

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Samenvatting

A multicore architecture is configured to exploit explicit task parallelism to save power by sharing interrupt sources that trigger independent tasks.

Originele taal-2Engels
OctrooinummerUS2015143141
IPCG06F 13/ 24 A I
Prioriteitsdatum18/11/13
StatusGepubliceerd - 21 mei 2015

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