Reduction of large resistor networks

J. Rommes, P.T.J. Lenaers, W.H.A. Schilders

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

Samenvatting

Electro Static Discharge (ESD) analysis is of vital importance during the design of large-scale integrated circuits, since it gives insight in how well the interconnect can handle unintended peak charges. Due to the increasing amount of interconnect and metal layers, ESD analysis may become very time consuming or even unfeasible. We propose an algorithm for the reduction of large resistor networks, that typically arise during ESD, to much smaller equivalent networks. Experiments show reduction and speed-ups up to a factor 10.
Originele taal-2Engels
TitelScientific Computing in Electrical Engineering SCEE 2008
RedacteurenJ. Roos, L.R.J. Costa
Plaats van productieBerlin
UitgeverijSpringer
Pagina's555-562
ISBN van geprinte versie978-3-642-12293-4
DOI's
StatusGepubliceerd - 2010

Publicatie series

NaamMathematics in Industry
Volume14
ISSN van geprinte versie1612-3956

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