Reaching intrinsic compute efficiency requires adaptable micro-architectures

M. Wijtvliet; L.J.W. Waeijen; M. Adriaansen; H. Corporaal

Reaching intrinsic compute efficiency requires adaptable micro-architectures

M. Wijtvliet, L.J.W. Waeijen, M. Adriaansen, H. Corporaal

Onderzoeksoutput: Bijdrage aan congres › Paper › Academic

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Today’s embedded applications demand high compute performance at a tight energy budget, which requires a high compute efficiency. Compute efficiency is upper-bound by the technology node, however in practice programmable devices are orders of magnitude away from achieving this intrinsic compute efficiency. This work investigates the sources of inefficiency that cause this, and identifies four key design guidelines that can steer compute efficiency towards sub-picojoule per operation. Based on these guidelines a novel architecture with adaptive micro-architecture, and accompanying tool flow is proposed.

Originele taal-2	Engels
Pagina's	1-7
Aantal pagina's	7
Status	Gepubliceerd - 18 jan. 2016
Evenement	9th International Workshop on Programmability and Architectures for Heterogeneous Multicores (MULTIPROG-2016), January 18, 2016, Prague, Czech Republic - Prague, Tsjechië Duur: 18 jan. 2016 → 18 jan. 2016 http://research.ac.upc.edu/multiprog/

Workshop

Workshop	9th International Workshop on Programmability and Architectures for Heterogeneous Multicores (MULTIPROG-2016), January 18, 2016, Prague, Czech Republic
Verkorte titel	MULTIPROG-2016
Land/Regio	Tsjechië
Stad	Prague
Periode	18/01/16 → 18/01/16
Internet adres	http://research.ac.upc.edu/multiprog/

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Reaching intrinsic compute efficiency requires adaptable micro-architectures. / Wijtvliet, M.; Waeijen, L.J.W.; Adriaansen, M. et al.
2016. 1-7 Paper gepresenteerd op 9th International Workshop on Programmability and Architectures for Heterogeneous Multicores (MULTIPROG-2016), January 18, 2016, Prague, Czech Republic, Prague, Tsjechië.

Onderzoeksoutput: Bijdrage aan congres › Paper › Academic

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AU - Corporaal, H.

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N2 - Today’s embedded applications demand high compute performance at a tight energy budget, which requires a high compute efficiency. Compute efficiency is upper-bound by the technology node, however in practice programmable devices are orders of magnitude away from achieving this intrinsic compute efficiency. This work investigates the sources of inefficiency that cause this, and identifies four key design guidelines that can steer compute efficiency towards sub-picojoule per operation. Based on these guidelines a novel architecture with adaptive micro-architecture, and accompanying tool flow is proposed.

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KW - spatial layout

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Reaching intrinsic compute efficiency requires adaptable micro-architectures

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