Re-addressing SRAM design and measurement for sub-threshold operation in view of classic 6T vs. standard cell based implementations

Xin Fan, Jan Stuijt, Rui Wang, Bo Liu, Tobias Gemmeke

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

2 Citaten (Scopus)

Samenvatting

This paper re-addresses standard-cell based SRAM design for sub-threshold operation. Rather than using flip-flop or latch gates to implement SRAM bitcells, a circuit structure that is fully based on combinational logic, OAI (Or-And-Invert) and AOI (And-Or-Invert) gates, is presented. Measurements on a 90-kb 40-nm SRAM chip show that, the OAI/AOI-based SRAM operates at a minimum access voltage of 410 mV and obtains a minimum read energy of 30 fJ per access per bit. At the data retention voltage of 330 mV, it features a leakage power of 1.6 pW per bit. Taking the proposed SRAM and a classic 6T-cell design as examples, the relationship between yield and bias in key figures of merit of a SRAM is highlighted based on silicon measurement results. This motivates a statistical view on the evaluation of SRAMs operating in sub-threshold.

Originele taal-2Engels
TitelProceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017 : March 14-15, 2017, Santa Clara, California USA
Plaats van productiePiscataway
UitgeverijIEEE Computer Society
Pagina's65-70
Aantal pagina's6
ISBN van elektronische versie978-1-5090-5404-6
ISBN van geprinte versie978-1-5090-5405-3
DOI's
StatusGepubliceerd - 2 mei 2017
Extern gepubliceerdJa
Evenement18th International Symposium on Quality Electronic Design, ISQED 2017 - Santa Clara, Verenigde Staten van Amerika
Duur: 14 mrt 201715 mrt 2017

Congres

Congres18th International Symposium on Quality Electronic Design, ISQED 2017
Land/RegioVerenigde Staten van Amerika
StadSanta Clara
Periode14/03/1715/03/17

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