Predictive timing error calibration technique for RF current-streering DACs

Y. Tang, J.A. Hegt, A.H.M. Roermund, van

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

Samenvatting

Timing errors become more dominant in dynamic performance in high-resolution Radio Frequency DACs. It consumes a lot of power and area to reduce timing errors below picoseconds. To relax the requirements on circuit design and layout complexity, a predictive timing error calibration technique based on on-chip timing error measurement is demonstrated in this work. Matlab behavior level simulation shows that this on-chip calibration technique can improve the SFDR significantly in a 2GS/s DAC. Simulation results of a phase detector, the key circuit in this calibration technique, are given. The circuit is designed in a CMOS 90nm process.
Originele taal-2Engels
TitelProceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2008) 18 - 21 May 2008, Seattle, Washington, USA
Plaats van productiePiscataway, New Jersy, USA
UitgeverijInstitute of Electrical and Electronics Engineers
Pagina's228-231
ISBN van geprinte versie978-1-424-41683-7
StatusGepubliceerd - 2008
Evenement2008 IEEE International Symposium on Circuits and Systems (ISCAS 2008) - Seattle, Verenigde Staten van Amerika
Duur: 18 mei 200821 mei 2008

Congres

Congres2008 IEEE International Symposium on Circuits and Systems (ISCAS 2008)
Verkorte titelISCAS 2008
Land/RegioVerenigde Staten van Amerika
StadSeattle
Periode18/05/0821/05/08
AnderISCAS 2008, Seattle, Washington, USA

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