Power supply noise and ground bounce aware pattern generation for delay testing

A. Todri, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

2 Citaten (Scopus)

Samenvatting

Power supply noise and ground bounce can significantly impact the circuit's performance. Existing delay testing techniques do not capture the impact of combined and uncorrelated power supply noise and ground bounce for critical path delay analysis. They capture the worst case power supply noise in order to obtain the worst case path delay. We show that such assumption is not necessarily sufficient and combined effects of both power and ground noise should be considered for path delay analysis. First, we propose accurate close-form mathematical models for capturing the path delay variations in the presence of power supply noise and ground bounce. We utilize these models as the fitness function for pattern generation technique which is a simulated annealing based iterative process. In our experiments, we show that path delay variation can be significant if test patterns are not properly selected.
Originele taal-2Engels
Titel2011 IEEE 9th International New Circuits and systems conference
UitgeverijIEEE/LEOS
Pagina's73-76
Aantal pagina's4
ISBN van geprinte versie978-1-61284-136-6
DOI's
StatusGepubliceerd - 29 jun. 2011
Extern gepubliceerdJa
Evenement2011 IEEE 9th International New Circuits and systems conference - Bordeaux, France
Duur: 26 jun. 201129 jun. 2011

Congres

Congres2011 IEEE 9th International New Circuits and systems conference
Periode26/06/1129/06/11

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