Post-silicon validation of yield-aware analog circuit synthesis

Engin Afacan, Gönenç Berkol, Günhan Dündar

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

Samenvatting

Analog/RF circuit design automation tools have become more popular in recent years. Conventionally, evolutionary algorithms are employed during circuit sizing and layout generation processes; thus, time to design can be considerably reduced. Furthermore, yield-aware analog circuit design automation tools have been developed by integrating variability analysis with the optimization. Previous works have mostly focused on improving the efficiency of optimization tools without sacrificing the accuracy. However, the accuracy of design automation tools is still argumentative since they are validated either at the pre- or post- layout level. But, in practice, post-silicon measurement is mandatory in order to verify the robustness of synthesis tools. To our best knowledge, there is no implementation and verification of yield-aware circuit sizing tools in the literature. In this study, a yield-aware circuit sizing tool is validated on silicon. For that purpose, two different OTA circuits were optimized using a yield-aware circuit sizing tool, a test chip was designed, taped-out, characterized, and results were compared with the results generated by the optimizer.

Originele taal-2Engels
TitelSMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings
Plaats van productiePiscataway
UitgeverijInstitute of Electrical and Electronics Engineers
Pagina's245-248
Aantal pagina's4
ISBN van elektronische versie978-1-7281-1201-5
DOI's
StatusGepubliceerd - 1 jul 2019
Evenement16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2019 - Lausanne, Zwitserland
Duur: 15 jul 201918 jul 2019

Congres

Congres16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2019
Land/RegioZwitserland
StadLausanne
Periode15/07/1918/07/19

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