Post-silicon validation of yield-aware analog circuit synthesis

Analog/RF circuit design automation tools have become more popular in recent years. Conventionally, evolutionary algorithms are employed during circuit sizing and layout generation processes; thus, time to design can be considerably reduced. Furthermore, yield-aware analog circuit design automation tools have been developed by integrating variability analysis with the optimization. Previous works have mostly focused on improving the efficiency of optimization tools without sacrificing the accuracy. However, the accuracy of design automation tools is still argumentative since they are validated either at the pre- or post- layout level. But, in practice, post-silicon measurement is mandatory in order to verify the robustness of synthesis tools. To our best knowledge, there is no implementation and verification of yield-aware circuit sizing tools in the literature. In this study, a yield-aware circuit sizing tool is validated on silicon. For that purpose, two different OTA circuits were optimized using a yield-aware circuit sizing tool, a test chip was designed, taped-out, characterized, and results were compared with the results generated by the optimizer.