Performance-efficient architecture for free-viewpoint 3DTV receiver

E. Bondarev; S. Zinger; P.H.N. With, de

doi:10.1109/ICCE.2010.5418923

Performance-efficient architecture for free-viewpoint 3DTV receiver

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

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This paper presents algorithmic and architectural solutions for a free-viewpoint 3DTV receiver system. We describe our rendering algorithm and evaluate performance-related challenges in mapping of the algorithm on a receiver board of which the architecture is outlined. It is found that the required processing load exceeds the provisioning of dual Virtex5 FPGAs. We develop several mapping optimizations to fit the rendering algorithm into a platform.

Originele taal-2	Engels
Titel	Proceedings of the 28th International Conference on Consumer Electronics (ICCE), 9-13 January 2010, Las Vegas, Nevada
Plaats van productie	Piscataway
Uitgeverij	Institute of Electrical and Electronics Engineers
Pagina's	65-66
ISBN van elektronische versie	978-1-4244-4316-1
ISBN van geprinte versie	978-1-4244-4314-7
DOI's	https://doi.org/10.1109/ICCE.2010.5418923
Status	Gepubliceerd - 2010
Evenement	2010 IEEE International Conference on Consumer Electronics, ICCE 2010 - Las Vegas, Verenigde Staten van Amerika Duur: 11 jan. 2010 → 13 jan. 2010

Congres

Congres	2010 IEEE International Conference on Consumer Electronics, ICCE 2010
Verkorte titel	ICCE 2010
Land/Regio	Verenigde Staten van Amerika
Stad	Las Vegas
Periode	11/01/10 → 13/01/10
Ander	IEEE International Conference on Consumer Electronics (ICCE 10)

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10.1109/ICCE.2010.5418923

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@inproceedings{548adfa62fa54d7b9f7fc553e10a6547,

title = "Performance-efficient architecture for free-viewpoint 3DTV receiver",

abstract = "This paper presents algorithmic and architectural solutions for a free-viewpoint 3DTV receiver system. We describe our rendering algorithm and evaluate performance-related challenges in mapping of the algorithm on a receiver board of which the architecture is outlined. It is found that the required processing load exceeds the provisioning of dual Virtex5 FPGAs. We develop several mapping optimizations to fit the rendering algorithm into a platform.",

author = "E. Bondarev and S. Zinger and \{With, de\}, P.H.N.",

year = "2010",

doi = "10.1109/ICCE.2010.5418923",

language = "English",

isbn = "978-1-4244-4314-7",

pages = "65--66",

booktitle = "Proceedings of the 28th International Conference on Consumer Electronics (ICCE), 9-13 January 2010, Las Vegas, Nevada",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "2010 IEEE International Conference on Consumer Electronics, ICCE 2010, ICCE 2010 ; Conference date: 11-01-2010 Through 13-01-2010",

}

Bondarev, E , Zinger, S & With, de, PHN 2010, Performance-efficient architecture for free-viewpoint 3DTV receiver. in Proceedings of the 28th International Conference on Consumer Electronics (ICCE), 9-13 January 2010, Las Vegas, Nevada. Institute of Electrical and Electronics Engineers, Piscataway, blz. 65-66, 2010 IEEE International Conference on Consumer Electronics, ICCE 2010, Las Vegas, Nevada, Verenigde Staten van Amerika, 11/01/10. https://doi.org/10.1109/ICCE.2010.5418923

Performance-efficient architecture for free-viewpoint 3DTV receiver. / Bondarev, E.; Zinger, S.; With, de, P.H.N.
Proceedings of the 28th International Conference on Consumer Electronics (ICCE), 9-13 January 2010, Las Vegas, Nevada. Piscataway: Institute of Electrical and Electronics Engineers, 2010. blz. 65-66.

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

TY - GEN

T1 - Performance-efficient architecture for free-viewpoint 3DTV receiver

AU - Bondarev, E.

AU - Zinger, S.

AU - With, de, P.H.N.

PY - 2010

Y1 - 2010

N2 - This paper presents algorithmic and architectural solutions for a free-viewpoint 3DTV receiver system. We describe our rendering algorithm and evaluate performance-related challenges in mapping of the algorithm on a receiver board of which the architecture is outlined. It is found that the required processing load exceeds the provisioning of dual Virtex5 FPGAs. We develop several mapping optimizations to fit the rendering algorithm into a platform.

AB - This paper presents algorithmic and architectural solutions for a free-viewpoint 3DTV receiver system. We describe our rendering algorithm and evaluate performance-related challenges in mapping of the algorithm on a receiver board of which the architecture is outlined. It is found that the required processing load exceeds the provisioning of dual Virtex5 FPGAs. We develop several mapping optimizations to fit the rendering algorithm into a platform.

U2 - 10.1109/ICCE.2010.5418923

DO - 10.1109/ICCE.2010.5418923

M3 - Conference contribution

SN - 978-1-4244-4314-7

SP - 65

EP - 66

BT - Proceedings of the 28th International Conference on Consumer Electronics (ICCE), 9-13 January 2010, Las Vegas, Nevada

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 2010 IEEE International Conference on Consumer Electronics, ICCE 2010

Y2 - 11 January 2010 through 13 January 2010

ER -

Performance-efficient architecture for free-viewpoint 3DTV receiver

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