Optimization of programmable logic arrays

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We describe two techniques for the minimization of the area of a Programmable Logic Array (PLA). Based on the logic functions to be implemented an assignment of the inputs and outputs to the columns of a PLA is determined that is especially suited for row segmentation. An upper bound and a lower bound for the number of rows in the segmented PLA are derived. Furthermore, it is shown how the result can be improved upon by the duplication of some of the inputs.
Originele taal-2Engels
Pagina's (van-tot)149-162
Aantal pagina's14
TijdschriftIntegration : the VLSI Journal
Nummer van het tijdschrift2
StatusGepubliceerd - 1984

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