Foundry services for photonic integration enable access to such technologies and facilitate fab-less businesses models. The technologies are sufficiently mature for proof-of-concept demonstrators, advanced prototypes, and two-medium small-volume production. Further improvement of the technology processes behind those services requires extensive research and development efforts in order to advance the foundry offerings and assure scalability, process control, and the yield required for volume production. A high-level automation of test and assembly processes in the PIC manufacturing chain is essential to improve statistical process control and scalability of all processes. These allow for early known-good-die identification, optimization of fabrication process window, improved yield, and volume production. In this paper we propose a standardized approach to chip layout that supports automated test and assembly processes already at the design phase. Moreover, we describe a modular test software framework based on open standards. Within this test framework, standard file formats for chip, equipment, and measurement description, and the open file formats for storage and exchange of data are described. This test framework is a part of the openEPDA initiative and enables test automation, user-defined testing, data analysis, exchangeability, and traceability across the full manufacturing chain from design to product.
|Tijdschrift||IEEE Journal of Selected Topics in Quantum Electronics|
|Nummer van het tijdschrift||5|
|Status||Gepubliceerd - 1 sep 2019|