On synthesis of reduced order models

A framework for model reduction and synthesis is presented, which enables the re-use of reduced order models in circuit simulation. Two synthesis techniques are considered for obtaining the circuit representation (netlist) of the reduced model: (1) by means of realizing the reduced transfer function and (2) by unstamping the reduced system matrices. For both methods, advantages and limitations are discussed. Especially when model reduction exploits structure preservation, we show that using the model as a current-driven element is possible, and allows for synthesis without controlled sources. The presented framework serves as a basis for reduction of large parasitic R/RC/RCL networks.