On-chip test infrastructure design for optimal multi-site testing

In this chapter, we propose to optimise the throughput for both wafer test and final test by means of multi-site testing. For wafer test, we maximise the throughput by testing a relatively large number of sites through a narrow enhanced-RPCT (E-RPCT) interface. For final test, we contact all SoC pins, and hence the number of multi sites is limited. We present a generic throughput model for multi-site testing, valid for both wafer test and final test, which considers the effects of test time, index time, abort-on-fail and re-test after contact fails. Subsequently, we present an algorithm that for a given SoC with a fixed target ATE and a probe station, designs and optimises an on-chip test infrastructure, DfT, that allows for maximal-throughput wafer-level multi-site testing. In case the given SoC uses a flattened top-level test, our algorithm determines the design of an E-RPCT. In case the given SoC uses a modular test approach, in addition to the E-RPCT wrapper, the algorithm determines the on-chip test architecture consisting of test access mechanisms (TAMs) and core wrappers. Next, we present a second algorithm that for a given fixed ATE and SoC handler, and for the SoC with DfT optimised for wafer testing, determines the multi-site number for maximal throughput at final test.