On approximate reduction of multi-port resistor networks

M. Ugryumova, J. Rommes, W.H.A. Schilders

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

Samenvatting

Simulation of the influence of interconnect structures and substrates is essential for a good understanding of modern chip behavior. Sometimes such simulations are not feasible with current circuit simulators. We propose an approach to reduce the large resistor networks obtained from extraction of the parasitic effects that builds upon the work in (Rommes and Schilders, IEEE Trans. CAD Circ. Syst. 29:28–39, 2010). The novelty in our approach is that we obtain improved reductions, by developing error estimations which enable to delete superfluous resistors and to control accuracy. An industrial test case demonstrates the potential of the new method.
Originele taal-2Engels
TitelProceedings of the 8th Conference on Scientific Computing in Electrical Engineering (SCEE 2010, Toulouse, France, September 19-24, 2012)
RedacteurenB. Michielsen, J.R. Poirier
Plaats van productieBerlin
UitgeverijSpringer
Pagina's377-385
ISBN van geprinte versie978-3-642-22452-2
DOI's
StatusGepubliceerd - 2012
Evenementconference; SCEE 2010; 2010-09-19; 2010-09-24 -
Duur: 19 sep 201024 sep 2010

Publicatie series

NaamMathematics in Industry
Volume16
ISSN van geprinte versie1612-3956

Congres

Congresconference; SCEE 2010; 2010-09-19; 2010-09-24
Periode19/09/1024/09/10
AnderSCEE 2010

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