Novel damage model for delamination in Cu/low-k IC backend structures

For the development of state-of-the-art Cu/low-k CMOS technologies, the integration and introduction of new low-k materials are one of the major bottlenecks due to the bad thermal and mechanical integrity of these materials and the inherited weak interfacial adhesion. Especially the forces resulting from packaging related processes such as dicing, wire bonding, bumping and molding are critical and can easily result in cracking, delamination and chipping of the IC back-end structure if no appropriate measures are taken. This paper presents a methodology for optimizing the thermo-mechanical reliability of bond pads by using a 3D multi-level Finite Element approach. An important characteristic of this methodology is the use of a novel energy-based damage model, which allows a fast qualitative comparison of different back-end structures. The usability of the methodology will be illustrated by the comparison of three different bond pad structures.