Neuromorphic architectures for spiking deep neural networks

Giacomo Indiveri; Federico Corradi; Ning Qiao

doi:10.1109/IEDM.2015.7409623

Neuromorphic architectures for spiking deep neural networks

Giacomo Indiveri
, Federico Corradi
, Ning Qiao

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

130 Citaten (Scopus)

Samenvatting

We present a full custom hardware implementation of a deep neural network, built using multiple neuromorphic VLSI devices that integrate analog neuron and synapse circuits together with digital asynchronous logic circuits. The deep network comprises an event-based convolutional stage for feature extraction connected to a spike-based learning stage for feature classification. We describe the properties of the chips used to implement the network and present preliminary experimental results that validate the approach proposed.

Originele taal-2	Engels
Titel	2015 IEEE International Electron Devices Meeting (IEDM)
Uitgeverij	Institute of Electrical and Electronics Engineers
Aantal pagina's	1
ISBN van elektronische versie	978-1-4673-9894-7
DOI's	https://doi.org/10.1109/IEDM.2015.7409623
Status	Gepubliceerd - 18 feb. 2016
Extern gepubliceerd	Ja
Evenement	2015 IEEE International Electron Devices Meeting (IEDM) - Washington, Verenigde Staten van Amerika Duur: 7 dec. 2015 → 9 dec. 2015 Congresnummer: 61

Congres

Congres	2015 IEEE International Electron Devices Meeting (IEDM)
Verkorte titel	IEDM 2015
Land/Regio	Verenigde Staten van Amerika
Stad	Washington
Periode	7/12/15 → 9/12/15

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10.1109/IEDM.2015.7409623

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@inproceedings{e1431b5c271c43668c813dc5eeeeb7bf,

title = "Neuromorphic architectures for spiking deep neural networks",

abstract = "We present a full custom hardware implementation of a deep neural network, built using multiple neuromorphic VLSI devices that integrate analog neuron and synapse circuits together with digital asynchronous logic circuits. The deep network comprises an event-based convolutional stage for feature extraction connected to a spike-based learning stage for feature classification. We describe the properties of the chips used to implement the network and present preliminary experimental results that validate the approach proposed.",

keywords = "Neurons, Integrated circuit modeling, Neuromorphics, Voltage control, Adaptation models, Feature extraction, Computer architecture",

author = "Giacomo Indiveri and Federico Corradi and Ning Qiao",

year = "2016",

month = feb,

day = "18",

doi = "10.1109/IEDM.2015.7409623",

language = "English",

booktitle = "2015 IEEE International Electron Devices Meeting (IEDM)",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "2015 IEEE International Electron Devices Meeting, IEDM 2015, IEDM 2015 ; Conference date: 07-12-2015 Through 09-12-2015",

}

Indiveri, G, Corradi, F & Qiao, N 2016, Neuromorphic architectures for spiking deep neural networks. in 2015 IEEE International Electron Devices Meeting (IEDM)., 7409623, Institute of Electrical and Electronics Engineers, 2015 IEEE International Electron Devices Meeting (IEDM), Washington, Washington, Verenigde Staten van Amerika, 7/12/15. https://doi.org/10.1109/IEDM.2015.7409623

TY - GEN

T1 - Neuromorphic architectures for spiking deep neural networks

AU - Indiveri, Giacomo

AU - Corradi, Federico

AU - Qiao, Ning

N1 - Conference code: 61

PY - 2016/2/18

Y1 - 2016/2/18

N2 - We present a full custom hardware implementation of a deep neural network, built using multiple neuromorphic VLSI devices that integrate analog neuron and synapse circuits together with digital asynchronous logic circuits. The deep network comprises an event-based convolutional stage for feature extraction connected to a spike-based learning stage for feature classification. We describe the properties of the chips used to implement the network and present preliminary experimental results that validate the approach proposed.

AB - We present a full custom hardware implementation of a deep neural network, built using multiple neuromorphic VLSI devices that integrate analog neuron and synapse circuits together with digital asynchronous logic circuits. The deep network comprises an event-based convolutional stage for feature extraction connected to a spike-based learning stage for feature classification. We describe the properties of the chips used to implement the network and present preliminary experimental results that validate the approach proposed.

KW - Neurons

KW - Integrated circuit modeling

KW - Neuromorphics

KW - Voltage control

KW - Adaptation models

KW - Feature extraction

KW - Computer architecture

U2 - 10.1109/IEDM.2015.7409623

DO - 10.1109/IEDM.2015.7409623

M3 - Conference contribution

BT - 2015 IEEE International Electron Devices Meeting (IEDM)

PB - Institute of Electrical and Electronics Engineers

T2 - 2015 IEEE International Electron Devices Meeting, IEDM 2015

Y2 - 7 December 2015 through 9 December 2015

ER -

Neuromorphic architectures for spiking deep neural networks

Samenvatting

Congres

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