Multi-level nanoimprint lithography for large-area thin film transistor backplane manufacturing

Thin film transistors (TFTs) are the basis for current AMOLED display arrays. For next-generation displays, higher resolution and cost-effective manufacturing of panels is adamant. The current benchmark patterning method in the display industry is photolithography. Here, we propose the use of a hybrid approach of nanoimprint lithography and conventional FPD processing for the realization of high-resolution display backplanes. We demonstrate the realization of sub-micron amorphous oxide semiconductor TFTs with multi-level nanoimprint lithography in order to decrease the number of patterning steps in display manufacturing. Top-gate self-aligned a-IGZO TFTs are realized with performance comparable to benchmark photolithography-based TFTs.