Method for improving writability of SRAM memory

V. Sharma; S. Cosemans; W. Dehaene; F. Catthoor; M. Ashouei; J. Huisken

Method for improving writability of SRAM memory

V. Sharma (Uitvinder)
, S. Cosemans (Uitvinder)
, W. Dehaene (Uitvinder)
, F. Catthoor (Uitvinder)
, M. Ashouei (Uitvinder)
, J. Huisken (Uitvinder)

Onderzoeksoutput: Octrooi › Octrooi-publicatie

Samenvatting

A method for improving writability of an SRAM cell is disclosed. In one aspect, the method includes applying a first voltage higher than the global ground voltage and a third voltage higher than the global supply voltage to the ground supply nodes of the invertors of the SRAM cell, pre-charging one of the complementary bitlines to the global ground voltage, and applying a second voltage higher than the global supply voltage to the access transistors during a write operation to the SRAM cell.

Originele taal-2	Engels
Octrooinummer	US2012063211
IPC	G11C 11/ 00 A I
Prioriteitsdatum	13/09/11
Status	Gepubliceerd - 15 mrt. 2012
Extern gepubliceerd	Ja

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@misc{e2b9992ff9de49658b4cf9571aa0a6bf,

title = "Method for improving writability of SRAM memory",

abstract = "A method for improving writability of an SRAM cell is disclosed. In one aspect, the method includes applying a first voltage higher than the global ground voltage and a third voltage higher than the global supply voltage to the ground supply nodes of the invertors of the SRAM cell, pre-charging one of the complementary bitlines to the global ground voltage, and applying a second voltage higher than the global supply voltage to the access transistors during a write operation to the SRAM cell.",

author = "V. Sharma and S. Cosemans and W. Dehaene and F. Catthoor and M. Ashouei and J. Huisken",

year = "2012",

month = mar,

day = "15",

language = "English",

type = "Patent",

note = "US2012063211; G11C 11/ 00 A I",

}

TY - PAT

T1 - Method for improving writability of SRAM memory

AU - Sharma, V.

AU - Cosemans, S.

AU - Dehaene, W.

AU - Catthoor, F.

AU - Ashouei, M.

AU - Huisken, J.

PY - 2012/3/15

Y1 - 2012/3/15

N2 - A method for improving writability of an SRAM cell is disclosed. In one aspect, the method includes applying a first voltage higher than the global ground voltage and a third voltage higher than the global supply voltage to the ground supply nodes of the invertors of the SRAM cell, pre-charging one of the complementary bitlines to the global ground voltage, and applying a second voltage higher than the global supply voltage to the access transistors during a write operation to the SRAM cell.

AB - A method for improving writability of an SRAM cell is disclosed. In one aspect, the method includes applying a first voltage higher than the global ground voltage and a third voltage higher than the global supply voltage to the ground supply nodes of the invertors of the SRAM cell, pre-charging one of the complementary bitlines to the global ground voltage, and applying a second voltage higher than the global supply voltage to the access transistors during a write operation to the SRAM cell.

M3 - Patent publication

M1 - US2012063211

ER -

Method for improving writability of SRAM memory

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