Mapping a VLIW x SIMD processor on an FGA : scalability and performance

M. Nelissen; C.H. Berkel, van; S. Sawitzki

doi:10.1109/FPL.2007.4380707

Mapping a VLIW x SIMD processor on an FGA : scalability and performance

M. Nelissen, C.H. Berkel, van, S. Sawitzki

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

Samenvatting

This paper describes VPF, a VLIW SIMD processor architecture developed to demonstrate the possibilities and limitations of the modern FPGA devices with respect to vector processing. VPF is developed in a bottom-up manner, using some specific Xilinx Virtex-4 device features to achieve 200 MHz performance for vector widths up to 16 issuing one VLIW instruction per clock cycle. The theoretical peak performance of VPF is 1.2·10^9 vector operations per second. For classical real-world DSP benchmarks around 1...3·10^8 vector operations per second can be achieved.

Originele taal-2	Engels
Titel	Proceedings of the 17th International Conference on Field Programmable Logic and Applications 2007 (FPL 2007) 27-29 August 2007, Amsterdam, The Netherlands
Plaats van productie	Piscataway, New Jersey, USA
Uitgeverij	Institute of Electrical and Electronics Engineers
Pagina's	521-524
ISBN van geprinte versie	1-4244-1060-6
DOI's	https://doi.org/10.1109/FPL.2007.4380707
Status	Gepubliceerd - 2007
Evenement	conference; FPL 2007, Amsterdam, The Netherlands; 2007-08-27; 2007-08-29 - Duur: 27 aug. 2007 → 29 aug. 2007

Congres

Congres	conference; FPL 2007, Amsterdam, The Netherlands; 2007-08-27; 2007-08-29
Periode	27/08/07 → 29/08/07
Ander	FPL 2007, Amsterdam, The Netherlands

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10.1109/FPL.2007.4380707

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Nelissen, M., Berkel, van, C. H., & Sawitzki, S. (2007). Mapping a VLIW x SIMD processor on an FGA : scalability and performance. In Proceedings of the 17th International Conference on Field Programmable Logic and Applications 2007 (FPL 2007) 27-29 August 2007, Amsterdam, The Netherlands (blz. 521-524). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/FPL.2007.4380707

Nelissen, M. ; Berkel, van, C.H. ; Sawitzki, S. / Mapping a VLIW x SIMD processor on an FGA : scalability and performance. Proceedings of the 17th International Conference on Field Programmable Logic and Applications 2007 (FPL 2007) 27-29 August 2007, Amsterdam, The Netherlands. Piscataway, New Jersey, USA : Institute of Electrical and Electronics Engineers, 2007. blz. 521-524

@inproceedings{e7f2c5b7900640658eab99032a12f012,

title = "Mapping a VLIW x SIMD processor on an FGA : scalability and performance",

abstract = "This paper describes VPF, a VLIW SIMD processor architecture developed to demonstrate the possibilities and limitations of the modern FPGA devices with respect to vector processing. VPF is developed in a bottom-up manner, using some specific Xilinx Virtex-4 device features to achieve 200 MHz performance for vector widths up to 16 issuing one VLIW instruction per clock cycle. The theoretical peak performance of VPF is 1.2·10^9 vector operations per second. For classical real-world DSP benchmarks around 1...3·10^8 vector operations per second can be achieved.",

author = "M. Nelissen and {Berkel, van}, C.H. and S. Sawitzki",

year = "2007",

doi = "10.1109/FPL.2007.4380707",

language = "English",

isbn = "1-4244-1060-6",

pages = "521--524",

booktitle = "Proceedings of the 17th International Conference on Field Programmable Logic and Applications 2007 (FPL 2007) 27-29 August 2007, Amsterdam, The Netherlands",

publisher = "Institute of Electrical and Electronics Engineers",

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note = "conference; FPL 2007, Amsterdam, The Netherlands; 2007-08-27; 2007-08-29 ; Conference date: 27-08-2007 Through 29-08-2007",

}

Nelissen, M, Berkel, van, CH & Sawitzki, S 2007, Mapping a VLIW x SIMD processor on an FGA : scalability and performance. in Proceedings of the 17th International Conference on Field Programmable Logic and Applications 2007 (FPL 2007) 27-29 August 2007, Amsterdam, The Netherlands. Institute of Electrical and Electronics Engineers, Piscataway, New Jersey, USA, blz. 521-524, conference; FPL 2007, Amsterdam, The Netherlands; 2007-08-27; 2007-08-29, 27/08/07. https://doi.org/10.1109/FPL.2007.4380707

Mapping a VLIW x SIMD processor on an FGA : scalability and performance. / Nelissen, M.; Berkel, van, C.H.; Sawitzki, S.
Proceedings of the 17th International Conference on Field Programmable Logic and Applications 2007 (FPL 2007) 27-29 August 2007, Amsterdam, The Netherlands. Piscataway, New Jersey, USA: Institute of Electrical and Electronics Engineers, 2007. blz. 521-524.

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

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AU - Sawitzki, S.

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N2 - This paper describes VPF, a VLIW SIMD processor architecture developed to demonstrate the possibilities and limitations of the modern FPGA devices with respect to vector processing. VPF is developed in a bottom-up manner, using some specific Xilinx Virtex-4 device features to achieve 200 MHz performance for vector widths up to 16 issuing one VLIW instruction per clock cycle. The theoretical peak performance of VPF is 1.2·10^9 vector operations per second. For classical real-world DSP benchmarks around 1...3·10^8 vector operations per second can be achieved.

AB - This paper describes VPF, a VLIW SIMD processor architecture developed to demonstrate the possibilities and limitations of the modern FPGA devices with respect to vector processing. VPF is developed in a bottom-up manner, using some specific Xilinx Virtex-4 device features to achieve 200 MHz performance for vector widths up to 16 issuing one VLIW instruction per clock cycle. The theoretical peak performance of VPF is 1.2·10^9 vector operations per second. For classical real-world DSP benchmarks around 1...3·10^8 vector operations per second can be achieved.

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M3 - Conference contribution

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BT - Proceedings of the 17th International Conference on Field Programmable Logic and Applications 2007 (FPL 2007) 27-29 August 2007, Amsterdam, The Netherlands

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Nelissen M, Berkel, van CH, Sawitzki S. Mapping a VLIW x SIMD processor on an FGA : scalability and performance. In Proceedings of the 17th International Conference on Field Programmable Logic and Applications 2007 (FPL 2007) 27-29 August 2007, Amsterdam, The Netherlands. Piscataway, New Jersey, USA: Institute of Electrical and Electronics Engineers. 2007. blz. 521-524 doi: 10.1109/FPL.2007.4380707

Mapping a VLIW x SIMD processor on an FGA : scalability and performance

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