Samenvatting
Recent research has demonstrated that for certain types of applications like sampled audio systems, self-timed circuits can achieve very low power consumption, because unused circuit parts automatically turn into a stand-by mode. Additional savings may be obtained by combining the self-timed circuits with a mechanism that adaptively adjusts the supply voltage to the smallest possible, while maintaining the performance requirements. This paper describes such a mechanism, analyzes the possible power savings, and presents a demonstrator chip that has been fabricated and tested. The idea of voltage scaling has been used previously in synchronous circuits, and the contributions of the present paper are: 1) the combination of supply scaling and self-timed circuitry which has some unique advantages, and 2) the thorough analysis of the power savings that are possible using this technique.
| Originele taal-2 | Engels |
|---|---|
| Titel | Low-Power CMOS Design |
| Redacteuren | Anantha Chandrakasan, Robert Brodersen |
| Uitgeverij | Wiley-IEEE |
| Pagina's | 150-156 |
| Aantal pagina's | 7 |
| ISBN van elektronische versie | 9780470545058 |
| ISBN van geprinte versie | 9780780334298 |
| DOI's | |
| Status | Gepubliceerd - 1 jan. 1998 |
| Extern gepubliceerd | Ja |
Bibliografische nota
Publisher Copyright:© 1998 the Institute of electrical and electronics engineers, Inc. All rights reserved.
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