Low-power operation using self-timed circuits and adaptive scaling of the supply voltage

Lars S. Nielsen, Cees Niessen, Jens SparsØ, Kees Van Berkel

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureHoofdstukAcademicpeer review

Samenvatting

Recent research has demonstrated that for certain types of applications like sampled audio systems, self-timed circuits can achieve very low power consumption, because unused circuit parts automatically turn into a stand-by mode. Additional savings may be obtained by combining the self-timed circuits with a mechanism that adaptively adjusts the supply voltage to the smallest possible, while maintaining the performance requirements. This paper describes such a mechanism, analyzes the possible power savings, and presents a demonstrator chip that has been fabricated and tested. The idea of voltage scaling has been used previously in synchronous circuits, and the contributions of the present paper are: 1) the combination of supply scaling and self-timed circuitry which has some unique advantages, and 2) the thorough analysis of the power savings that are possible using this technique.

Originele taal-2Engels
TitelLow-Power CMOS Design
RedacteurenAnantha Chandrakasan, Robert Brodersen
UitgeverijWiley-IEEE
Pagina's150-156
Aantal pagina's7
ISBN van elektronische versie9780470545058
ISBN van geprinte versie9780780334298
DOI's
StatusGepubliceerd - 1 jan. 1998
Extern gepubliceerdJa

Bibliografische nota

Publisher Copyright:
© 1998 the Institute of electrical and electronics engineers, Inc. All rights reserved.

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