Low energy FPGA interconnect design

R. Krishnan, J. Pineda de Gyvez, M. Bennebroek

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

3 Citaten (Scopus)
1 Downloads (Pure)


We propose a new low energy FPGA interconnect fabric that is based on low energy switch blocks using Dynamic Threshold CMOS (DTMOS) based switches and an encoded-low swing (EL) technique. The presented case study illustrates that the encoded-low swing technique and Dual Threshold MOS based switches results in 41% energy reduction compared to the conventional technique using full swing signalling and NMOS pass transistor based switches. We also show through a theoretical analysis, that a certain timing budget can be met by the EL technique, using 11% more buffered switches, but still consuming 62% less energy than conventional techniques. Circuit simulations, taking also the transmitter and receiver complexity into account, are in line with the model results and indicate that a timing budget can be met at 30% less energy consumption. All our results are based on CMOS 0.13µ process technology and are done using a transistor level simulator.
Originele taal-2Engels
TitelProceedings of the 2004 ACM Great Lake Symposium of VLSI, Boston, April 2004
StatusGepubliceerd - 2004


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