Interconnect-aware mapping of applications to coarse-grain reconfigurable architectures

N. Bansal, Sumit Gupta, N.D. Dutt, A. Nicolau, R. Gupta

    Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

    11 Citaten (Scopus)

    Samenvatting

    Coarse-grain reconfigurable architectures consist of a large number of processing elements (PEs) connected together in a network. For mapping applications to such coarse-grain architectures, we present an algorithm that takes into account the number and delay of interconnects. This algorithm maps operations to PEs and data transfers to interconnects in the fabric. We explore three different cost functions that largely affect the performance of the scheduler: (a) priority of the operations, (b) affinity of operations to PEs based on past mapping decisions, and (c) connectivity between the PEs. Our results show that a priority-based operation cost function coupled with a connectivity-based PE cost function gives results that are close to the lower bounds for a range of designs.
    Originele taal-2Engels
    TitelField Programmable Logic and Applications (14th International Conference, FPL 2004, Leuven, Belgium, August 30-September 1, 2004. Proceedings)
    RedacteurenJ. Becker, M. Platzner, S. Vernalde
    Plaats van productieBerlin
    UitgeverijSpringer
    Pagina's891-899
    ISBN van geprinte versie3-540-22989-2
    DOI's
    StatusGepubliceerd - 2004

    Publicatie series

    NaamLecture Notes in Computer Science
    Volume3203
    ISSN van geprinte versie0302-9743

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