Integrated test support features for multi-GHz DACs in 28nm CMOS

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

2 Downloads (Pure)

Samenvatting

This paper presents a 7GSps 6b current-steering DAC in 28nm CMOS for VLSI SoC embedding which includes on-chip memory and clock generation circuits for wafer-sort testing. Several linearization techniques are implemented to extend linearity to very high frequencies with levels of SFDR>50dB for signals up to 1GHz, while keeping the DAC footprint small - 0.035mm². Testing at full speed is facilitated by means of integrating a digital front-end BIST scheme in 0.048mm². It uses a 5kbit 8X TI data memory, based on circular shift registers to avoid signal-dependent disturbances. An integrated 7 GHz CML ring oscillator type clock generator, as well as a serial data interface, simplify and reduce the cost of testing the DAC at high-speed.
Originele taal-2Engels
TitelTVHSAC: IEEE International Workshop on Test and Validation of High Speed Analog Circuits Anaheim, CA, USA
Aantal pagina's3
StatusGepubliceerd - 13 sep 2013
EvenementTVHSAC: IEEE International Workshop on Test and Validation of High Speed Analog Circuits - Anaheim, Verenigde Staten van Amerika
Duur: 8 sep 201313 sep 2013

Congres

CongresTVHSAC: IEEE International Workshop on Test and Validation of High Speed Analog Circuits
LandVerenigde Staten van Amerika
StadAnaheim
Periode8/09/1313/09/13

    Vingerafdruk

Citeer dit

Quinn, P., Radulov, G. I., & van Roermund, A. H. M. (2013). Integrated test support features for multi-GHz DACs in 28nm CMOS. In TVHSAC: IEEE International Workshop on Test and Validation of High Speed Analog Circuits Anaheim, CA, USA