Impact of process scaling on 1/f noise in advanced CMOS technologies

M. J. Knitel; P. H. Woerlee; A. J. Scholten; A. T.A. Zegers-Van Duijnhoven

doi:10.1109/IEDM.2000.904356

Impact of process scaling on 1/f noise in advanced CMOS technologies

M. J. Knitel, P. H. Woerlee, A. J. Scholten, A. T.A. Zegers-Van Duijnhoven

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

43 Citaties (SciVal)

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The influence of the gate-oxide thickness, the substrate dope, and the gate bias on the input-referred spectral 1/f noise density Sv_gate has been experimentally investigated. It is shown that the dependence on the oxide thickness and the gate bias can be described by the model of Hung, and that Sv_gate can be predicted for future technologies. Discrepancies with the ITRS roadmap are discussed.

Originele taal-2	Engels
Titel	2000 IEEE International Electron Devices Meeting
Plaats van productie	Piscataway
Uitgeverij	Institute of Electrical and Electronics Engineers
Pagina's	463-466
Aantal pagina's	4
ISBN van geprinte versie	0-7803-6438-4
DOI's	https://doi.org/10.1109/IEDM.2000.904356
Status	Gepubliceerd - 1 dec. 2000
Extern gepubliceerd	Ja
Evenement	2000 IEEE International Electron Devices Meeting, IEDM 2000 - San Francisco, Verenigde Staten van Amerika Duur: 10 dec. 2000 → 13 dec. 2000

Congres

Congres	2000 IEEE International Electron Devices Meeting, IEDM 2000
Land/Regio	Verenigde Staten van Amerika
Stad	San Francisco
Periode	10/12/00 → 13/12/00

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title = "Impact of process scaling on 1/f noise in advanced CMOS technologies",

abstract = "The influence of the gate-oxide thickness, the substrate dope, and the gate bias on the input-referred spectral 1/f noise density Svgate has been experimentally investigated. It is shown that the dependence on the oxide thickness and the gate bias can be described by the model of Hung, and that Svgate can be predicted for future technologies. Discrepancies with the ITRS roadmap are discussed.",

author = "Knitel, {M. J.} and Woerlee, {P. H.} and Scholten, {A. J.} and {Zegers-Van Duijnhoven}, {A. T.A.}",

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Knitel, MJ, Woerlee, PH, Scholten, AJ & Zegers-Van Duijnhoven, ATA 2000, Impact of process scaling on 1/f noise in advanced CMOS technologies. in 2000 IEEE International Electron Devices Meeting. Institute of Electrical and Electronics Engineers, Piscataway, blz. 463-466, 2000 IEEE International Electron Devices Meeting, IEDM 2000, San Francisco, California, Verenigde Staten van Amerika, 10/12/00. https://doi.org/10.1109/IEDM.2000.904356

Impact of process scaling on 1/f noise in advanced CMOS technologies. / Knitel, M. J.; Woerlee, P. H.; Scholten, A. J. et al.
2000 IEEE International Electron Devices Meeting. Piscataway: Institute of Electrical and Electronics Engineers, 2000. blz. 463-466.

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

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AU - Woerlee, P. H.

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AB - The influence of the gate-oxide thickness, the substrate dope, and the gate bias on the input-referred spectral 1/f noise density Svgate has been experimentally investigated. It is shown that the dependence on the oxide thickness and the gate bias can be described by the model of Hung, and that Svgate can be predicted for future technologies. Discrepancies with the ITRS roadmap are discussed.

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Impact of process scaling on 1/f noise in advanced CMOS technologies

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