Impact of etch stop layer on negative bias illumination stress of amorphous indium gallium zinc oxide transistors

A. Bhoolokam, M. Nag, A. Chasin, S. Steudel, J. Genoe, G. Gelinck, G. Groeseneken, P. Heremans

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

2 Citaten (Scopus)

Samenvatting

In this work we show that the negative bias illumination stress (NBIS) of amorphous Indium Gallium Zinc Oxide (a-IGZO) transistors with an etch stop layer (ESL) deposited by physical vapor deposition (PVD) is substantially better than the NBIS of devices where the ESL layer is deposited by plasma enhanced chemical vapor deposition (PECVD). Both devices show similar transistor characteristics and bias stress in the dark but under NBIS conditions at 425 nm, PVD ESL based transistors show much less threshold voltage shift. The reduction in deep defects due to passivation by PVD layer is responsible for improved performance under NBIS.

Originele taal-2Engels
Titel2014 44th European Solid State Device Research Conference (ESSDERC) 22-26 Sept. 2014, Palazzo del Casinò, Venezia Lido, Italy
RedacteurenR. Bez
Plaats van productiePiscataway
UitgeverijIEEE Computer Society
Pagina's302-304
Aantal pagina's3
ISBN van elektronische versie978-1-4799-4376-0
ISBN van geprinte versie978-1-4799-4378-4
DOI's
StatusGepubliceerd - 5 nov 2014
Extern gepubliceerdJa
Evenement44th European Solid-State Device Research Conference (ESSDERC 2014) - Palazzo del Casinò, Venezia, Italië
Duur: 22 sep 201426 sep 2014
Congresnummer: 44
http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6926646

Congres

Congres44th European Solid-State Device Research Conference (ESSDERC 2014)
Verkorte titelESSDERC 2014
Land/RegioItalië
StadVenezia
Periode22/09/1426/09/14
Internet adres

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