High-value MOS capacitor arrays in ultradeep trenches in silicon

F. Roozeboom; R. Elfrink; J. Verhoeven; J. Van den Meerakker; F. Holthuysen

doi:10.1016/S0167-9317(00)00383-X

High-value MOS capacitor arrays in ultradeep trenches in silicon

F. Roozeboom, R. Elfrink, J. Verhoeven, J. Van den Meerakker, F. Holthuysen

Onderzoeksoutput: Bijdrage aan tijdschrift › Congresartikel › peer review

35 Citaten (Scopus)

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A fully Si-compatible process has been developed to manufacture 6-inch silicon (100) wafers with patterns of trenches, several hundreds of μm deep with a pitch of a few μm. The hundred-fold enlarged silicon surface is used as a substrate for MOS (Metal-Oxide-Semiconductor) capacitor arrays with a capacitance of 1 nF to 1 μF. The specific capacitance was as high as 100 nF/mm².

Originele taal-2	Engels
Pagina's (van-tot)	581-584
Aantal pagina's	4
Tijdschrift	Microelectronic Engineering
Volume	53
Nummer van het tijdschrift	1
DOI's	https://doi.org/10.1016/S0167-9317(00)00383-X
Status	Gepubliceerd - 1 jan. 2000
Extern gepubliceerd	Ja
Evenement	25th International Conference on Micro- and Nano-Engineering - Rome, Italy Duur: 21 sep. 1999 → 23 sep. 1999

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title = "High-value MOS capacitor arrays in ultradeep trenches in silicon",

abstract = "A fully Si-compatible process has been developed to manufacture 6-inch silicon (100) wafers with patterns of trenches, several hundreds of μm deep with a pitch of a few μm. The hundred-fold enlarged silicon surface is used as a substrate for MOS (Metal-Oxide-Semiconductor) capacitor arrays with a capacitance of 1 nF to 1 μF. The specific capacitance was as high as 100 nF/mm2.",

author = "F. Roozeboom and R. Elfrink and J. Verhoeven and {Van den Meerakker}, J. and F. Holthuysen",

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AU - Roozeboom, F.

AU - Elfrink, R.

AU - Verhoeven, J.

AU - Van den Meerakker, J.

AU - Holthuysen, F.

PY - 2000/1/1

Y1 - 2000/1/1

N2 - A fully Si-compatible process has been developed to manufacture 6-inch silicon (100) wafers with patterns of trenches, several hundreds of μm deep with a pitch of a few μm. The hundred-fold enlarged silicon surface is used as a substrate for MOS (Metal-Oxide-Semiconductor) capacitor arrays with a capacitance of 1 nF to 1 μF. The specific capacitance was as high as 100 nF/mm2.

AB - A fully Si-compatible process has been developed to manufacture 6-inch silicon (100) wafers with patterns of trenches, several hundreds of μm deep with a pitch of a few μm. The hundred-fold enlarged silicon surface is used as a substrate for MOS (Metal-Oxide-Semiconductor) capacitor arrays with a capacitance of 1 nF to 1 μF. The specific capacitance was as high as 100 nF/mm2.

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U2 - 10.1016/S0167-9317(00)00383-X

DO - 10.1016/S0167-9317(00)00383-X

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T2 - 25th International Conference on Micro- and Nano-Engineering

Y2 - 21 September 1999 through 23 September 1999

ER -

High-value MOS capacitor arrays in ultradeep trenches in silicon

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