High performance 0.13 um CMOS with classical architecture

J. Schmitz; A. C.M.C. Van Brandenburg; E. J.H. Collart; L. H.M. Huijten; A. H. Montree; Y. V. Ponomarev; R. F.M. Roes; A. J. Scholten; P. H. Woerlee

High performance 0.13 um CMOS with classical architecture

J. Schmitz
, A. C.M.C. Van Brandenburg
, E. J.H. Collart
, L. H.M. Huijten
, A. H. Montree
, Y. V. Ponomarev
, R. F.M. Roes
, A. J. Scholten
, P. H. Woerlee

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

Samenvatting

We present high performance 0.13 μm CMOS devices fabricated with classical methods. It is shown that the application of low-energy ion implantation, regular (pure) SiO₂ gate oxide, standard polysilicon, and RTP anneals result in reliable and robust transistor performance.

Originele taal-2	Engels
Titel	ESSDERC 1998 - Proceedings of the 28th European Solid-State Device Research Conference
Redacteuren	A. Touboul, Y. Danto, H. Grunbacher
Uitgeverij	IEEE Computer Society
Pagina's	156-159
Aantal pagina's	4
ISBN van geprinte versie	2863322346
Status	Gepubliceerd - 1 jan. 1998
Extern gepubliceerd	Ja
Evenement	28th European Solid-State Device Research Conference, ESSDERC 1998 - Bordeaux, Frankrijk Duur: 8 sep. 1998 → 10 sep. 1998

Congres

Congres	28th European Solid-State Device Research Conference, ESSDERC 1998
Land/Regio	Frankrijk
Stad	Bordeaux
Periode	8/09/98 → 10/09/98

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Schmitz, J., Van Brandenburg, A. C. M. C., Collart, E. J. H., Huijten, L. H. M., Montree, A. H., Ponomarev, Y. V., Roes, R. F. M., Scholten, A. J., & Woerlee, P. H. (1998). High performance 0.13 um CMOS with classical architecture. In A. Touboul, Y. Danto, & H. Grunbacher (editors), ESSDERC 1998 - Proceedings of the 28th European Solid-State Device Research Conference (blz. 156-159). Artikel 1503512 IEEE Computer Society.

@inproceedings{92498296dba144d095be67fcb149cb33,

title = "High performance 0.13 um CMOS with classical architecture",

abstract = "We present high performance 0.13 μm CMOS devices fabricated with classical methods. It is shown that the application of low-energy ion implantation, regular (pure) SiO2 gate oxide, standard polysilicon, and RTP anneals result in reliable and robust transistor performance.",

author = "J. Schmitz and \{Van Brandenburg\}, \{A. C.M.C.\} and Collart, \{E. J.H.\} and Huijten, \{L. H.M.\} and Montree, \{A. H.\} and Ponomarev, \{Y. V.\} and Roes, \{R. F.M.\} and Scholten, \{A. J.\} and Woerlee, \{P. H.\}",

year = "1998",

month = jan,

day = "1",

language = "English",

isbn = "2863322346",

pages = "156--159",

editor = "A. Touboul and Y. Danto and H. Grunbacher",

booktitle = "ESSDERC 1998 - Proceedings of the 28th European Solid-State Device Research Conference",

publisher = "IEEE Computer Society",

address = "United States",

note = "28th European Solid-State Device Research Conference, ESSDERC 1998 ; Conference date: 08-09-1998 Through 10-09-1998",

}

Schmitz, J, Van Brandenburg, ACMC, Collart, EJH, Huijten, LHM, Montree, AH, Ponomarev, YV, Roes, RFM, Scholten, AJ & Woerlee, PH 1998, High performance 0.13 um CMOS with classical architecture. in A Touboul, Y Danto & H Grunbacher (reds.), ESSDERC 1998 - Proceedings of the 28th European Solid-State Device Research Conference., 1503512, IEEE Computer Society, blz. 156-159, 28th European Solid-State Device Research Conference, ESSDERC 1998, Bordeaux, Frankrijk, 8/09/98.

High performance 0.13 um CMOS with classical architecture. / Schmitz, J.; Van Brandenburg, A. C.M.C.; Collart, E. J.H. et al.
ESSDERC 1998 - Proceedings of the 28th European Solid-State Device Research Conference. reds. / A. Touboul; Y. Danto; H. Grunbacher. IEEE Computer Society, 1998. blz. 156-159 1503512.

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

TY - GEN

T1 - High performance 0.13 um CMOS with classical architecture

AU - Schmitz, J.

AU - Van Brandenburg, A. C.M.C.

AU - Collart, E. J.H.

AU - Huijten, L. H.M.

AU - Montree, A. H.

AU - Ponomarev, Y. V.

AU - Roes, R. F.M.

AU - Scholten, A. J.

AU - Woerlee, P. H.

PY - 1998/1/1

Y1 - 1998/1/1

N2 - We present high performance 0.13 μm CMOS devices fabricated with classical methods. It is shown that the application of low-energy ion implantation, regular (pure) SiO2 gate oxide, standard polysilicon, and RTP anneals result in reliable and robust transistor performance.

AB - We present high performance 0.13 μm CMOS devices fabricated with classical methods. It is shown that the application of low-energy ion implantation, regular (pure) SiO2 gate oxide, standard polysilicon, and RTP anneals result in reliable and robust transistor performance.

UR - https://www.scopus.com/pages/publications/84908222441

M3 - Conference contribution

AN - SCOPUS:84908222441

SN - 2863322346

SP - 156

EP - 159

BT - ESSDERC 1998 - Proceedings of the 28th European Solid-State Device Research Conference

A2 - Touboul, A.

A2 - Danto, Y.

A2 - Grunbacher, H.

PB - IEEE Computer Society

T2 - 28th European Solid-State Device Research Conference, ESSDERC 1998

Y2 - 8 September 1998 through 10 September 1998

ER -

High performance 0.13 um CMOS with classical architecture

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Congres

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