High-level modeling of a high-speed flash A/D converter for mixed-signal simulations of digital telecommunication front-ends

J. Compiet, P.W.T. Jong, de, P. Wambacq, G. Vandersteen, S. Donnay, M. Engels, I. Bolsen

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

3 Citaten (Scopus)
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Samenvatting

A hierarchical high-level model of a high-speed flash ADC is presented. The input parameter list is extracted from a 400 MHz, 4-bit, flash ADC designed in HSPICE in a 0.35 µm CMOS technology. A speedup in simulation time of 5000 is reported compared to the 3-bit flash ADC HSPICE simulations. The accuracy of the model is verified with HSPICE simulations and shows a good agreement.
Originele taal-2Engels
TitelProc. IEEE Mixed-Signal Design, 2000. SSMSD. 2000 Southwest Symposium (SSMSD 2000), San Diego
Plaats van productieNew York
UitgeverijInstitute of Electrical and Electronics Engineers
Pagina's135-140
ISBN van geprinte versie0-7803-5975-5
DOI's
StatusGepubliceerd - 2000

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