Hierarchy-aware and area-efficient test infrastructure design for core-based system chips

A. Sehgal, S.K. Goel, E.J. Marinissen, K. Chakrabarty

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureHoofdstukAcademicpeer review

11 Citaten (Scopus)

Samenvatting

Multiple levels of design hierarchy are common in current-generation system-on-chip (SOC) integrated circuits. However, most prior work on test access mechanism (TAM) optimization and test scheduling is based on a flattened design hierarchy. We investigate hierarchy-aware test infrastructure design, wherein wrapper/TAM optimization and test scheduling are carried out for hierarchical SOCs for two practical design scenarios. In the first scenario, the wrapper and TAM implementation for the embedded child cores in hierarchical (parent) cores are delivered in a hard form by the core provider. In the second scenario, the wrapper and TAM architecture of the child cores embedded in the parent cores are implemented by the system integrator. Experimental results are presented for the ITC'02 SOC test benchmarks
Originele taal-2Engels
TitelProceedings Design, Automation and Test in Europe, 2006. DATE '06
Plaats van productiePIscataway
UitgeverijInstitute of Electrical and Electronics Engineers
Aantal pagina's6
ISBN van geprinte versie978-3-9810801-1-7, 3-9810801-1-4
DOI's
StatusGepubliceerd - 2006
Extern gepubliceerdJa
Evenement9th Design, Automation and Test in Europe Conference (DATE 2006) - Munich, Duitsland
Duur: 6 mrt 200610 mrt 2006
Congresnummer: 9

Congres

Congres9th Design, Automation and Test in Europe Conference (DATE 2006)
Verkorte titelDATE 2006
Land/RegioDuitsland
StadMunich
Periode6/03/0610/03/06

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