Glitch-free discretely programmable clock generation on chip

M. Meijer; F. Pessolano; J. Pineda de Gyvez

doi:10.1109/ISCAS.2005.1464968

Glitch-free discretely programmable clock generation on chip

M. Meijer
, F. Pessolano
, J. Pineda de Gyvez

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

284 Downloads (Pure)

Samenvatting

In this paper we describe a solution for a glitch-free discretely programmable clock generation unit (DPGC). The scheme is compatible with a GALS communication scheme in the sense that clock gating and clock pausing are possible. Besides, the proposed scheme does not require waiting for a new clock as the frequency change is seen as almost instantaneously. A prototype has been designed for a 0.13µm triple-well CMOS process technology to also study the properties of the scheme with respect to voltage scaling.

Originele taal-2	Engels
Titel	IEEE International Symposium on Circuits and Systems, 2005. ISCAS 2005, May 23-26 Kobe, Japan
Plaats van productie	Piscataway
Uitgeverij	Institute of Electrical and Electronics Engineers
Pagina's	1839-1842
ISBN van geprinte versie	0-7803-8834-8
DOI's	https://doi.org/10.1109/ISCAS.2005.1464968
Status	Gepubliceerd - 2005

Toegang tot document

10.1109/ISCAS.2005.1464968

Metis247718Definitieve gepubliceerde versie, 1,36 MB

Citeer dit

@inproceedings{8c2f6d9722a34b9b91456e3ef59f49a8,

title = "Glitch-free discretely programmable clock generation on chip",

abstract = "In this paper we describe a solution for a glitch-free discretely programmable clock generation unit (DPGC). The scheme is compatible with a GALS communication scheme in the sense that clock gating and clock pausing are possible. Besides, the proposed scheme does not require waiting for a new clock as the frequency change is seen as almost instantaneously. A prototype has been designed for a 0.13µm triple-well CMOS process technology to also study the properties of the scheme with respect to voltage scaling.",

author = "M. Meijer and F. Pessolano and \{Pineda de Gyvez\}, J.",

year = "2005",

doi = "10.1109/ISCAS.2005.1464968",

language = "English",

isbn = "0-7803-8834-8",

pages = "1839--1842",

booktitle = "IEEE International Symposium on Circuits and Systems, 2005. ISCAS 2005, May 23-26 Kobe, Japan",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

}

Glitch-free discretely programmable clock generation on chip. / Meijer, M.; Pessolano, F.; Pineda de Gyvez, J.
IEEE International Symposium on Circuits and Systems, 2005. ISCAS 2005, May 23-26 Kobe, Japan. Piscataway: Institute of Electrical and Electronics Engineers, 2005. blz. 1839-1842.

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

TY - GEN

T1 - Glitch-free discretely programmable clock generation on chip

AU - Meijer, M.

AU - Pessolano, F.

AU - Pineda de Gyvez, J.

PY - 2005

Y1 - 2005

N2 - In this paper we describe a solution for a glitch-free discretely programmable clock generation unit (DPGC). The scheme is compatible with a GALS communication scheme in the sense that clock gating and clock pausing are possible. Besides, the proposed scheme does not require waiting for a new clock as the frequency change is seen as almost instantaneously. A prototype has been designed for a 0.13µm triple-well CMOS process technology to also study the properties of the scheme with respect to voltage scaling.

AB - In this paper we describe a solution for a glitch-free discretely programmable clock generation unit (DPGC). The scheme is compatible with a GALS communication scheme in the sense that clock gating and clock pausing are possible. Besides, the proposed scheme does not require waiting for a new clock as the frequency change is seen as almost instantaneously. A prototype has been designed for a 0.13µm triple-well CMOS process technology to also study the properties of the scheme with respect to voltage scaling.

U2 - 10.1109/ISCAS.2005.1464968

DO - 10.1109/ISCAS.2005.1464968

M3 - Conference contribution

SN - 0-7803-8834-8

SP - 1839

EP - 1842

BT - IEEE International Symposium on Circuits and Systems, 2005. ISCAS 2005, May 23-26 Kobe, Japan

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

ER -

Glitch-free discretely programmable clock generation on chip

Samenvatting

Toegang tot document

Vingerafdruk

Citeer dit