Gate current and oxide reliability in p+ poly MOS capacitors with poly-Si and poly-Ge0.3Si0.7 gate material

C. Salm; J. H. Klootwijk; Y. Ponomarev; P. W.M. Boos; D. J. Gravesteijn; P. H. Woerlee

doi:10.1109/55.701420

Gate current and oxide reliability in p⁺ poly MOS capacitors with poly-Si and poly-Ge_0.3Si_0.7 gate material

C. Salm
, J. H. Klootwijk
, Y. Ponomarev
, P. W.M. Boos
, D. J. Gravesteijn
, P. H. Woerlee

Onderzoeksoutput: Bijdrage aan tijdschrift › Tijdschriftartikel › Academic › peer review

17 Citaten (Scopus)

Samenvatting

Fowler - Nordheim (FN) tunnel current and oxide reliability of PMOS capacitors with a p⁺ polycrystalline silicon (poly-Si) and polycrystalline germanium-silicon (poly-Ge_0.3Si_0.7) gate on 5.6-nm thick gate oxides have been compared. It is shown that the FN current depends on the gate material and the bias polarity. The tunneling barrier heights, φB, have been determined from FN-plots. The larger barrier height for negative bias, compared to positive bias, suggests that electron injection takes place from the valence band of the gate. This barrier height for the GeSi gate is 0.4 eV lower than for the Si gate due to the higher valence band edge position. Charge-to-breakdown (Q_bd) measurements show improved oxide reliability of the GeSi gate on of PMOS capacitors with 5.6 nm thick gate oxide. We confirm that workfunction engineering in deepsubmicron MOS technologies using poly-GeSi gates is possible without limiting effects of the gate currents and oxide reliability.

Originele taal-2	Engels
Pagina's (van-tot)	213-215
Aantal pagina's	3
Tijdschrift	IEEE Electron Device Letters
Volume	19
Nummer van het tijdschrift	7
DOI's	https://doi.org/10.1109/55.701420
Status	Gepubliceerd - 1 jul. 1998
Extern gepubliceerd	Ja

Financiering

Manuscript received April 30, 1997; revised February 17, 1998. This work was supported by the Dutch Foundation for Fundamental Research on Matter (FOM) and the Dutch Technology Foundation (STW). C. Salm is with MESA Research Institute, University of Twente, 7500 AE Enschede, The Netherlands. J. H. Klootwijk was with MESA Research Institute, University of Twente, 7500 AE Enschede, The Netherlands. He is now with Philips Research Laboratories, 5656 AA Eindhoven, The Netherlands. Y. Ponomarev and D. J. Gravesteijn are with Philips Research Laboratories, 5656 AA Eindhoven, The Netherlands. P. W. M. Boos was with MESA Research Institute, University of Twente, 7500 AE Enschede, The Netherlands. She is now with Philips Semiconductors, 6534 AE Nijmegen, The Netherlands. P. H. Woerlee is with MESA Research Institute, University of Twente, 7500 AE Enschede, The Netherlands and Philips Research Laboratories, 5656 AA Eindhoven, The Netherlands. Publisher Item Identifier S 0741-3106(98)04764-8.

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10.1109/55.701420

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@article{1c4423ddf9c44af49c104689488196d2,

title = "Gate current and oxide reliability in p+ poly MOS capacitors with poly-Si and poly-Ge0.3Si0.7 gate material",

abstract = "Fowler - Nordheim (FN) tunnel current and oxide reliability of PMOS capacitors with a p+ polycrystalline silicon (poly-Si) and polycrystalline germanium-silicon (poly-Ge0.3Si0.7) gate on 5.6-nm thick gate oxides have been compared. It is shown that the FN current depends on the gate material and the bias polarity. The tunneling barrier heights, φB, have been determined from FN-plots. The larger barrier height for negative bias, compared to positive bias, suggests that electron injection takes place from the valence band of the gate. This barrier height for the GeSi gate is 0.4 eV lower than for the Si gate due to the higher valence band edge position. Charge-to-breakdown (Qbd) measurements show improved oxide reliability of the GeSi gate on of PMOS capacitors with 5.6 nm thick gate oxide. We confirm that workfunction engineering in deepsubmicron MOS technologies using poly-GeSi gates is possible without limiting effects of the gate currents and oxide reliability.",

keywords = "Deep-submicron MOS technology, Fowler-Nordheim, GeSi, Oxide reliability, Valence band tunneling",

author = "C. Salm and Klootwijk, \{J. H.\} and Y. Ponomarev and Boos, \{P. W.M.\} and Gravesteijn, \{D. J.\} and Woerlee, \{P. H.\}",

year = "1998",

month = jul,

day = "1",

doi = "10.1109/55.701420",

language = "English",

volume = "19",

pages = "213--215",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers",

number = "7",

}

TY - JOUR

T1 - Gate current and oxide reliability in p+ poly MOS capacitors with poly-Si and poly-Ge0.3Si0.7 gate material

AU - Salm, C.

AU - Klootwijk, J. H.

AU - Ponomarev, Y.

AU - Boos, P. W.M.

AU - Gravesteijn, D. J.

AU - Woerlee, P. H.

PY - 1998/7/1

Y1 - 1998/7/1

N2 - Fowler - Nordheim (FN) tunnel current and oxide reliability of PMOS capacitors with a p+ polycrystalline silicon (poly-Si) and polycrystalline germanium-silicon (poly-Ge0.3Si0.7) gate on 5.6-nm thick gate oxides have been compared. It is shown that the FN current depends on the gate material and the bias polarity. The tunneling barrier heights, φB, have been determined from FN-plots. The larger barrier height for negative bias, compared to positive bias, suggests that electron injection takes place from the valence band of the gate. This barrier height for the GeSi gate is 0.4 eV lower than for the Si gate due to the higher valence band edge position. Charge-to-breakdown (Qbd) measurements show improved oxide reliability of the GeSi gate on of PMOS capacitors with 5.6 nm thick gate oxide. We confirm that workfunction engineering in deepsubmicron MOS technologies using poly-GeSi gates is possible without limiting effects of the gate currents and oxide reliability.

AB - Fowler - Nordheim (FN) tunnel current and oxide reliability of PMOS capacitors with a p+ polycrystalline silicon (poly-Si) and polycrystalline germanium-silicon (poly-Ge0.3Si0.7) gate on 5.6-nm thick gate oxides have been compared. It is shown that the FN current depends on the gate material and the bias polarity. The tunneling barrier heights, φB, have been determined from FN-plots. The larger barrier height for negative bias, compared to positive bias, suggests that electron injection takes place from the valence band of the gate. This barrier height for the GeSi gate is 0.4 eV lower than for the Si gate due to the higher valence band edge position. Charge-to-breakdown (Qbd) measurements show improved oxide reliability of the GeSi gate on of PMOS capacitors with 5.6 nm thick gate oxide. We confirm that workfunction engineering in deepsubmicron MOS technologies using poly-GeSi gates is possible without limiting effects of the gate currents and oxide reliability.

KW - Deep-submicron MOS technology

KW - Fowler-Nordheim

KW - GeSi

KW - Oxide reliability

KW - Valence band tunneling

UR - https://www.scopus.com/pages/publications/0032121871

U2 - 10.1109/55.701420

DO - 10.1109/55.701420

M3 - Article

AN - SCOPUS:0032121871

SN - 0741-3106

VL - 19

SP - 213

EP - 215

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 7

ER -