FPGA Implementations of HEVC Inverse DCT Using High-Level Synthesis

Ercan Kalali; Ilker Hamzaoglu

doi:10.1109/DASIP.2015.7367262

FPGA Implementations of HEVC Inverse DCT Using High-Level Synthesis

Ercan Kalali
, Ilker Hamzaoglu

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

Originele taal-2	Engels
Titel	2015 Conference on Design and Architectures for Signal and Image Processing (DASIP)
Uitgeverij	Institute of Electrical and Electronics Engineers
Aantal pagina's	6
ISBN van elektronische versie	978-1-4673-7738-6
DOI's	https://doi.org/10.1109/DASIP.2015.7367262
Status	Gepubliceerd - 4 jan. 2016
Extern gepubliceerd	Ja
Evenement	9th Conference on Design and Architectures for Signal and Image Processing, DASIP 2015 - AGH University of Science and Technology, Kracow, Polen Duur: 23 sep. 2015 → 25 sep. 2015 Congresnummer: 9

Congres

Congres	9th Conference on Design and Architectures for Signal and Image Processing, DASIP 2015
Verkorte titel	DASIP 2015
Land/Regio	Polen
Stad	Kracow
Periode	23/09/15 → 25/09/15

Toegang tot document

10.1109/DASIP.2015.7367262

Citeer dit

@inproceedings{418c0d0cf50d44499a884951b66556cf,

title = "FPGA Implementations of HEVC Inverse DCT Using High-Level Synthesis",

keywords = "HEVC, IDCT, FPGA, high-level synthesis",

author = "Ercan Kalali and Ilker Hamzaoglu",

year = "2016",

month = jan,

day = "4",

doi = "10.1109/DASIP.2015.7367262",

language = "English",

booktitle = "2015 Conference on Design and Architectures for Signal and Image Processing (DASIP)",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "9th Conference on Design and Architectures for Signal and Image Processing, DASIP 2015, DASIP 2015 ; Conference date: 23-09-2015 Through 25-09-2015",

}

Kalali, E & Hamzaoglu, I 2016, FPGA Implementations of HEVC Inverse DCT Using High-Level Synthesis. in 2015 Conference on Design and Architectures for Signal and Image Processing (DASIP)., 7367262, Institute of Electrical and Electronics Engineers, 9th Conference on Design and Architectures for Signal and Image Processing, DASIP 2015, Kracow, Polen, 23/09/15. https://doi.org/10.1109/DASIP.2015.7367262

TY - GEN

T1 - FPGA Implementations of HEVC Inverse DCT Using High-Level Synthesis

AU - Kalali, Ercan

AU - Hamzaoglu, Ilker

N1 - Conference code: 9

PY - 2016/1/4

Y1 - 2016/1/4

KW - HEVC

KW - IDCT

KW - FPGA

KW - high-level synthesis

U2 - 10.1109/DASIP.2015.7367262

DO - 10.1109/DASIP.2015.7367262

M3 - Conference contribution

BT - 2015 Conference on Design and Architectures for Signal and Image Processing (DASIP)

PB - Institute of Electrical and Electronics Engineers

T2 - 9th Conference on Design and Architectures for Signal and Image Processing, DASIP 2015

Y2 - 23 September 2015 through 25 September 2015

ER -