FPGA based controller for large port count optical packet switches

N. Calabretta, A. Osers, J. Luo, H.J.S. Dorren

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademic

Samenvatting

We present an FPGA based label processor for in-band optical labels with a processing time independent of the number of label bits. This allows for implementing an optical packet switching architecture that scales to a large port count without compromising the latency. As proof-of-concept we have employed an FPGA board with 100 MHz clock to validate the operation of the label processor in a 160 Gb/s optical packet switching system. Experimental results show successful 3 label bits processing and 160 Gb/s packets switching with 1 dB power penalty and 470 ns of latency. Projections on the label processor performance by using more powerful FPGAs indicate that 60 label bits (260 optical addresses) can be processed within 31 ns. The low latency label processing technique can allow the implementation of intelligent systems for optimal routing of the packets in the optical domain.
Originele taal-2Engels
TitelProceedings of the 14th International Conference on Transparent Optical Networks (ICTON 2012), 2-5 July 2012 , Warwick, UK
Plaats van productiePiscataway
UitgeverijInstitute of Electrical and Electronics Engineers
Pagina's1-4
ISBN van geprinte versie978-1-4673-2227-0
DOI's
StatusGepubliceerd - 2012
Evenement14th International Conference on Transparent Optical Networks (ICTON 2012) - University of Warwick, Coventry, Verenigd Koninkrijk
Duur: 2 jul 20125 jul 2012
Congresnummer: 14
http://www.nit.eu/icton-2012

Congres

Congres14th International Conference on Transparent Optical Networks (ICTON 2012)
Verkorte titelICTON 2012
LandVerenigd Koninkrijk
StadCoventry
Periode2/07/125/07/12
Ander14th Conference on transparent optical networks (ICTON), 2-5 July 2012, Coverty England
Internet adres

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