Formal verification of unreliable failure detectors in partially synchronous systems

M. Atif, M.R. Mousavi, A.A.H. Osaiweran

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In this paper, we formally verify four algorithms proposed in [M. Larrea, S. Arévalo and A. Fernández, Efficient Algorithms to Implement Unreliable Failure Detectors in Partially Synchronous Systems, 1999]. Each algorithm is specified formally as a network of timed automata and is verified with respect to completeness and accuracy properties. Using the model-checking tool UPPAAL, we detect and report the occurrences of deadlock (for all algorithms) between each pair of non-faulty nodes due to buffer overflow in communication channels with arbitrarily large buffers. We propose one solution for deadlock avoidance. Moreover, we use one of the algorithms studied in this paper as a measure to compare the effectiveness of three model-checking tools, namely, UPPAAL, mCRL2 and FDR2. We also show that all algorithms satisfy their completeness and accuracy properties if the required number of processes remain operational.
Originele taal-2Engels
Plaats van productieEindhoven
UitgeverijTechnische Universiteit Eindhoven
Aantal pagina's21
StatusGepubliceerd - 2011

Publicatie series

NaamComputer science reports
ISSN van geprinte versie0926-4515


Citeer dit

Atif, M., Mousavi, M. R., & Osaiweran, A. A. H. (2011). Formal verification of unreliable failure detectors in partially synchronous systems. (Computer science reports; Vol. 1112). Eindhoven: Technische Universiteit Eindhoven.