Formal micro-architectural analysis of on-chip ring networks

Perry van Wesel, Julien Schmaltz

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/CongresprocedureConferentiebijdrageAcademicpeer review

1 Citaat (Scopus)

Samenvatting

In the realm of Multi-Processors System-on-Chip (MPSoC's), the Network-on-Chip (NoC) connecting all system components plays a crucial role in the overall correctness and performance of the system. Recent papers have proposed several ring based NoC solutions. The description and analysis of these micro-architectures are informal in nature. Text is used to argue about, e.g., deadlock freedom. For the first time, this paper proposes an environment for the formal modelling and analysis of such ring architectures with an emphasis on liveness properties. Our contribution includes a language to model ring micro-architectures, invariant generation techniques, deadlock freedom verification, and the application of our approach on a realistic case-study. The analysis reveals a possible deadlock not mentioned in the original paper.

Originele taal-2Engels
TitelProceedings of the 55th Annual Design Automation Conference, DAC 2018
Plaats van productieNew York
UitgeverijACM/IEEE
Aantal pagina's6
ISBN van geprinte versie978-1-4503-5700-5
DOI's
StatusGepubliceerd - 24 jun 2018
Evenement55th Annual Design Automation Conference, (DAC2018) - San Francisco, Verenigde Staten van Amerika
Duur: 24 jun 201829 jun 2018
https://dl.acm.org/citation.cfm?id=3195970

Congres

Congres55th Annual Design Automation Conference, (DAC2018)
Verkorte titelDAC2018
LandVerenigde Staten van Amerika
StadSan Francisco
Periode24/06/1829/06/18
Internet adres

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  • Citeer dit

    van Wesel, P., & Schmaltz, J. (2018). Formal micro-architectural analysis of on-chip ring networks. In Proceedings of the 55th Annual Design Automation Conference, DAC 2018 [94] ACM/IEEE. https://doi.org/10.1145/3195970.3196054