Fast time-domain simulation for reliable fault detection

Bratislav Tasić; Jos J. Dohmen; Rick Janssen; E. Jan W. ter Maten; Theo G.J. Beelen; Roland Pulch

Fast time-domain simulation for reliable fault detection

Bratislav Tasić, Jos J. Dohmen, Rick Janssen, E. Jan W. ter Maten, Theo G.J. Beelen, Roland Pulch

Center for Analysis, Scientific Computing & Appl.

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

2 Citaten (Scopus)

Samenvatting

Imperfections in manufacturing processes may cause unwanted connections (faults) that are added to the nominal, "golden", design of an electronic circuit. By fault simulation we simulate all situations: a huge number of new connections and each with many different values, up to the regime of large deviations, for the newly added element. We also consider "opens" (broken connections). A strategy is developed to efficiently simulate the faulty solutions until their moment of detection. We fully exploit the hierarchical structure of the circuit. Fast fault simulation is achieved in which the golden solution and all faulty solutions are calculated over the same time step.

Originele taal-2	Engels
Titel	Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
Plaats van productie	Piscataway
Uitgeverij	Institute of Electrical and Electronics Engineers
Pagina's	301-306
Aantal pagina's	6
ISBN van elektronische versie	9783981537062
Status	Gepubliceerd - 25 apr. 2016
Evenement	19th Design, Automation and Test in Europe Conference and Exhibition (DATE 2016) - ICC, Dresden, Duitsland Duur: 14 mrt. 2016 → 18 mrt. 2016 Congresnummer: 19 https://www.date-conference.com/date16/

Congres

Congres	19th Design, Automation and Test in Europe Conference and Exhibition (DATE 2016)
Verkorte titel	DATE 2016
Land/Regio	Duitsland
Stad	Dresden
Periode	14/03/16 → 18/03/16
Internet adres	https://www.date-conference.com/date16/

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title = "Fast time-domain simulation for reliable fault detection",

abstract = "Imperfections in manufacturing processes may cause unwanted connections (faults) that are added to the nominal, {"}golden{"}, design of an electronic circuit. By fault simulation we simulate all situations: a huge number of new connections and each with many different values, up to the regime of large deviations, for the newly added element. We also consider {"}opens{"} (broken connections). A strategy is developed to efficiently simulate the faulty solutions until their moment of detection. We fully exploit the hierarchical structure of the circuit. Fast fault simulation is achieved in which the golden solution and all faulty solutions are calculated over the same time step.",

author = "Bratislav Tasi{\'c} and Dohmen, {Jos J.} and Rick Janssen and {ter Maten}, {E. Jan W.} and Beelen, {Theo G.J.} and Roland Pulch",

year = "2016",

month = apr,

day = "25",

language = "English",

pages = "301--306",

booktitle = "Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "19th Design, Automation and Test in Europe Conference and Exhibition (DATE 2016), DATE 2016 ; Conference date: 14-03-2016 Through 18-03-2016",

url = "https://www.date-conference.com/date16/",

}

Tasić, B, Dohmen, JJ, Janssen, R, ter Maten, EJW, Beelen, TGJ & Pulch, R 2016, Fast time-domain simulation for reliable fault detection. in Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016., 7459327, Institute of Electrical and Electronics Engineers, Piscataway, blz. 301-306, 19th Design, Automation and Test in Europe Conference and Exhibition (DATE 2016), Dresden, Duitsland, 14/03/16.

Fast time-domain simulation for reliable fault detection. / Tasić, Bratislav; Dohmen, Jos J.; Janssen, Rick et al.
Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016. Piscataway: Institute of Electrical and Electronics Engineers, 2016. blz. 301-306 7459327.

Onderzoeksoutput: Hoofdstuk in Boek/Rapport/Congresprocedure › Conferentiebijdrage › Academic › peer review

TY - GEN

T1 - Fast time-domain simulation for reliable fault detection

AU - Tasić, Bratislav

AU - Dohmen, Jos J.

AU - Janssen, Rick

AU - ter Maten, E. Jan W.

AU - Beelen, Theo G.J.

AU - Pulch, Roland

N1 - Conference code: 19

PY - 2016/4/25

Y1 - 2016/4/25

N2 - Imperfections in manufacturing processes may cause unwanted connections (faults) that are added to the nominal, "golden", design of an electronic circuit. By fault simulation we simulate all situations: a huge number of new connections and each with many different values, up to the regime of large deviations, for the newly added element. We also consider "opens" (broken connections). A strategy is developed to efficiently simulate the faulty solutions until their moment of detection. We fully exploit the hierarchical structure of the circuit. Fast fault simulation is achieved in which the golden solution and all faulty solutions are calculated over the same time step.

AB - Imperfections in manufacturing processes may cause unwanted connections (faults) that are added to the nominal, "golden", design of an electronic circuit. By fault simulation we simulate all situations: a huge number of new connections and each with many different values, up to the regime of large deviations, for the newly added element. We also consider "opens" (broken connections). A strategy is developed to efficiently simulate the faulty solutions until their moment of detection. We fully exploit the hierarchical structure of the circuit. Fast fault simulation is achieved in which the golden solution and all faulty solutions are calculated over the same time step.

UR - http://www.scopus.com/inward/record.url?scp=84973660947&partnerID=8YFLogxK

UR - https://ieeexplore.ieee.org/document/7459327

M3 - Conference contribution

AN - SCOPUS:84973660947

SP - 301

EP - 306

BT - Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 19th Design, Automation and Test in Europe Conference and Exhibition (DATE 2016)

Y2 - 14 March 2016 through 18 March 2016

ER -

Fast time-domain simulation for reliable fault detection

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