F6: Power/performance optimization of many-core processor SoCs

As performance scaling per core continues to slow-down, designers are faced with a myriad of challenges in efficiently using the transistors available in modern processes. This Forum will address these next generation computing challenges in the context of highly-parallel manycore processors. The key design challenge in this manycore era is management and efficient use of resources across the layers of design hierarchy to provide power efficient high performance. System design challenges and tradeoffs will be discussed for both high performance platforms as well as mobile platforms. This will be followed by a discussion on power optimization of manycore systems, on-chip communication fabrics, system-level power managment for real-time applications, power and performance modeling of manycore systems and a discussion on physical design challenges. The forum concludes with a panel discussion providing the opportunity for participants to give feedback and ask questions.